[PATCH] D81638: AMDGPU/GlobalISel: Fix 96 and 128 local loads and stores

Mon Jun 29 16:06:29 PDT 2020

arsenm added inline comments.

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Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp:1316

+bool AMDGPUDAGToDAGISel::SelectDS128Bit8ByteAligned(SDValue Addr, SDValue &Base,
+                                                   SDValue &Offset0,
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mbrkusanin wrote:
> This is currently unsed but is required because of DS128Bit8ByteAligned pattern. Without the patternt GIsel does not know how to pick ds_read2/write2_b64.
> 
> Currently if ds_read/write_b128 are not legal because of alignment they will be broken down to 4 ds_read/write_b32 instructions and later combined in SILoadStoreOptimizer. It seems to me that is should be possible to tell ISel's lowerLoad and lowerStore to pick ds_read2/write2_b64 when appropriate with this pattern. But it would be easier if that was a separate patch.
This is basically the same as the splitting the 64-bit case into read2. Can you factor that to avoid duplicating all of this

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81638/new/

https://reviews.llvm.org/D81638