[llvm] af9cc2d - [PowerPC] Fix FeatureISA3_1 def in PPC.td to imply FeatureISA3_0.

[Lei Huang via llvm-commits]

Author: Lei Huang
Date: 2020-06-29T16:13:02-05:00
New Revision: af9cc2d2afe8cbb8dc3b309707f17597ce43071e

URL: https://github.com/llvm/llvm-project/commit/af9cc2d2afe8cbb8dc3b309707f17597ce43071e
DIFF: https://github.com/llvm/llvm-project/commit/af9cc2d2afe8cbb8dc3b309707f17597ce43071e.diff

LOG: [PowerPC] Fix FeatureISA3_1 def in PPC.td to imply FeatureISA3_0.

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPC.td

Removed: 
    


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diff  --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 95ab6edd9f3f..4a4e7f499399 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -208,7 +208,8 @@ def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
                                      "Enable instructions added in ISA 3.0.">;
 def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",
                                      "true",
-                                     "Enable instructions added in ISA 3.1.">;
+                                     "Enable instructions added in ISA 3.1.",
+                                     [FeatureISA3_0]>;
 def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
                                         "Enable POWER9 Altivec instructions",
                                         [FeatureISA3_0, FeatureP8Altivec]>;