[PATCH] D82792: [SVE][CodeGen] Legalisation of unpredicated load instructions

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin created this revision.
kmclaughlin added reviewers: sdesmalen, efriedma, david-arm.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, tschuett.
Herald added a project: LLVM.

When splitting a load of a scalable type, the new address is
calculated in SplitVecRes_LOAD using a vscale and an add instruction.

This patch also adds the reg + imm addressing mode for
unpredicated loads, and a DAG combiner fold to visitADD for vscale:

- Fold (add (vscale(C0)), (vscale(C1))) to (add (vscale(C0 + C1)))


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82792

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-ldst.ll

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