[PATCH] D82762: X86: Use MOV32r0 pseudo instead of directly emitting xor

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: craig.topper, aivchenk, mike.dvoretsky.
Herald added subscribers: hiraditya, wdng.
Herald added a project: LLVM.

This was producing reg = xor undef reg, undef reg. This looks similar
to a use of a value to define itself, and I want to disallow undef
uses for SSA virtual registers. If this were to use implicit_def,
there's no guarantee the two operands end up using the same register
(I think no guarantee exists even if the two operands start out as the
same register, but this was violated when I switched this to use an
explicit implicit_def). The MOV32r0 pseudo evidently exists to handle
this case, so use it instead. This was more work than I expected for
the 64-bit case, but I didn't see any helper for materializing a
64-bit 0.


https://reviews.llvm.org/D82762

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/shadow-stack.ll


Index: llvm/test/CodeGen/X86/shadow-stack.ll
===================================================================
--- llvm/test/CodeGen/X86/shadow-stack.ll
+++ llvm/test/CodeGen/X86/shadow-stack.ll
@@ -38,7 +38,7 @@
 ; X86_64-NEXT:    .cfi_offset %rbp, -16
 ; X86_64-NEXT:    movq _buf@{{.*}}(%rip), %rax
 ; X86_64-NEXT:    movq (%rax), %rax
-; X86_64-NEXT:    xorq %rdx, %rdx
+; X86_64-NEXT:    xorl %edx, %edx
 ; X86_64-NEXT:    rdsspq %rdx
 ; X86_64-NEXT:    testq %rdx, %rdx
 ; X86_64-NEXT:    je LBB0_5
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -32448,12 +32448,17 @@
   MBB->addSuccessor(checkSspMBB);
 
   // Initialize a register with zero.
-  Register ZReg = MRI.createVirtualRegister(PtrRC);
-  unsigned XorRROpc = (PVT == MVT::i64) ? X86::XOR64rr : X86::XOR32rr;
-  BuildMI(checkSspMBB, DL, TII->get(XorRROpc))
-      .addDef(ZReg)
-      .addReg(ZReg, RegState::Undef)
-      .addReg(ZReg, RegState::Undef);
+  Register ZReg = MRI.createVirtualRegister(&X86::GR32RegClass);
+  BuildMI(checkSspMBB, DL, TII->get(X86::MOV32r0), ZReg);
+
+  if (PVT == MVT::i64) {
+    Register TmpZReg = MRI.createVirtualRegister(PtrRC);
+    BuildMI(checkSspMBB, DL, TII->get(X86::SUBREG_TO_REG), TmpZReg)
+      .addImm(0)
+      .addReg(ZReg)
+      .addImm(X86::sub_32bit);
+    ZReg = TmpZReg;
+  }
 
   // Read the current SSP Register value to the zeroed register.
   Register SSPCopyReg = MRI.createVirtualRegister(PtrRC);


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