[PATCH] D82483: [SVE] Code generation for fixed length vector adds.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14797
+
+static SDValue getPredicateForVector(SelectionDAG &DAG, SDLoc &DL, EVT VT) {
+  if (VT.isFixedLengthVector())
----------------
paulwalker-arm wrote:
> sdesmalen wrote:
> > nit: is `getAllTruePredicate` not a better name given the value this function returns? (similar for `getAllTruePredicateFor(Scalable|FixedLength)Vector`)
> getPredicateForFixedLengthVector (and by extension getPredicateForVector) doesn't return an AllTrue predicate but rather a predicate with only the first VT.getNumElts() being true with everything else being false.
> 
> I think we're going to have a similar situation with types like <n x 2 x f32> so tried to avoid AllTrue since that's an artifact of our current ISEL rather than representative of what is actually going on.
Yes, that's actually what I meant with `AllTruePredicateForFixedLengthVector(..., EVT VT)` . The `ForFixedLengthVector` part (passed as `VT`) suggests to me that it returns a predicate that is all true for the lanes of the fixed-length vector, not beyond that.


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  https://reviews.llvm.org/D82483/new/

https://reviews.llvm.org/D82483