[llvm] ff5ccf2 - Revert "[sve][acle] Add reinterpret intrinsics for brain float."
Francesco Petrogalli via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 26 13:20:37 PDT 2020
Author: Francesco Petrogalli
Date: 2020-06-26T20:19:49Z
New Revision: ff5ccf258e297df29f32d6b5e4fa0a7b95c44f9c
URL: https://github.com/llvm/llvm-project/commit/ff5ccf258e297df29f32d6b5e4fa0a7b95c44f9c
DIFF: https://github.com/llvm/llvm-project/commit/ff5ccf258e297df29f32d6b5e4fa0a7b95c44f9c.diff
LOG: Revert "[sve][acle] Add reinterpret intrinsics for brain float."
This reverts commit a15722c5ce4759c12960fe434ee6bd8aac70bb16.
The commmit has to be reverted because I accidentally submit
https://reviews.llvm.org/D82501 without the C tests that were added in
an early version of the patch.
Added:
Modified:
clang/utils/TableGen/SveEmitter.cpp
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-bitcast.ll
Removed:
################################################################################
diff --git a/clang/utils/TableGen/SveEmitter.cpp b/clang/utils/TableGen/SveEmitter.cpp
index a02df1ce92af..45db0a60487e 100644
--- a/clang/utils/TableGen/SveEmitter.cpp
+++ b/clang/utils/TableGen/SveEmitter.cpp
@@ -248,13 +248,13 @@ class SVEEmitter {
const char *Type;
const char *BuiltinType;
};
- SmallVector<ReinterpretTypeInfo, 12> Reinterprets = {
+ SmallVector<ReinterpretTypeInfo, 11> Reinterprets = {
{"s8", "svint8_t", "q16Sc"}, {"s16", "svint16_t", "q8Ss"},
{"s32", "svint32_t", "q4Si"}, {"s64", "svint64_t", "q2SWi"},
{"u8", "svuint8_t", "q16Uc"}, {"u16", "svuint16_t", "q8Us"},
{"u32", "svuint32_t", "q4Ui"}, {"u64", "svuint64_t", "q2UWi"},
- {"f16", "svfloat16_t", "q8h"}, {"bf16", "svbfloat16_t", "q8y"},
- {"f32", "svfloat32_t", "q4f"}, {"f64", "svfloat64_t", "q2d"}};
+ {"f16", "svfloat16_t", "q8h"}, {"f32", "svfloat32_t", "q4f"},
+ {"f64", "svfloat64_t", "q2d"}};
RecordKeeper &Records;
llvm::StringMap<uint64_t> EltTypes;
@@ -1208,10 +1208,6 @@ void SVEEmitter::createHeader(raw_ostream &OS) {
for (auto ShortForm : { false, true } )
for (const ReinterpretTypeInfo &From : Reinterprets)
for (const ReinterpretTypeInfo &To : Reinterprets) {
- const bool IsBFloat = StringRef(From.Suffix).equals("bf16") ||
- StringRef(To.Suffix).equals("bf16");
- if (IsBFloat)
- OS << "#if defined(__ARM_FEATURE_SVE_BF16)\n";
if (ShortForm) {
OS << "__aio " << From.Type << " svreinterpret_" << From.Suffix;
OS << "(" << To.Type << " op) {\n";
@@ -1222,8 +1218,6 @@ void SVEEmitter::createHeader(raw_ostream &OS) {
OS << "#define svreinterpret_" << From.Suffix << "_" << To.Suffix
<< "(...) __builtin_sve_reinterpret_" << From.Suffix << "_"
<< To.Suffix << "(__VA_ARGS__)\n";
- if (IsBFloat)
- OS << "#endif /* #if defined(__ARM_FEATURE_SVE_BF16) */\n";
}
SmallVector<std::unique_ptr<Intrinsic>, 128> Defs;
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 7b807fd1c08a..bfffbe45d1cf 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1466,6 +1466,7 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
def : Pat<(nxv8f16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8f16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8f16 ZPR:$src)>;
+ def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8f16 ZPR:$src)>;
def : Pat<(nxv8f16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
@@ -1486,24 +1487,6 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
def : Pat<(nxv2f64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2f64 ZPR:$src)>;
}
- let Predicates = [IsLE, HasSVE, HasBF16] in {
- def : Pat<(nxv8bf16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
- def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
- def : Pat<(nxv8bf16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
- def : Pat<(nxv8bf16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
- def : Pat<(nxv8bf16 (bitconvert (nxv8f16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
- def : Pat<(nxv8bf16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
- def : Pat<(nxv8bf16 (bitconvert (nxv2f64 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
-
- def : Pat<(nxv16i8 (bitconvert (nxv8bf16 ZPR:$src))), (nxv16i8 ZPR:$src)>;
- def : Pat<(nxv8i16 (bitconvert (nxv8bf16 ZPR:$src))), (nxv8i16 ZPR:$src)>;
- def : Pat<(nxv4i32 (bitconvert (nxv8bf16 ZPR:$src))), (nxv4i32 ZPR:$src)>;
- def : Pat<(nxv2i64 (bitconvert (nxv8bf16 ZPR:$src))), (nxv2i64 ZPR:$src)>;
- def : Pat<(nxv8f16 (bitconvert (nxv8bf16 ZPR:$src))), (nxv8f16 ZPR:$src)>;
- def : Pat<(nxv4f32 (bitconvert (nxv8bf16 ZPR:$src))), (nxv4f32 ZPR:$src)>;
- def : Pat<(nxv2f64 (bitconvert (nxv8bf16 ZPR:$src))), (nxv2f64 ZPR:$src)>;
- }
-
def : Pat<(nxv16i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
def : Pat<(nxv16i1 (reinterpret_cast (nxv8i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
def : Pat<(nxv16i1 (reinterpret_cast (nxv4i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
diff --git a/llvm/test/CodeGen/AArch64/sve-bitcast.ll b/llvm/test/CodeGen/AArch64/sve-bitcast.ll
index 670c9864c85a..ab70dea81d45 100644
--- a/llvm/test/CodeGen/AArch64/sve-bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/sve-bitcast.ll
@@ -340,118 +340,3 @@ define <vscale x 2 x double> @bitcast_float_to_double(<vscale x 4 x float> %v) {
%bc = bitcast <vscale x 4 x float> %v to <vscale x 2 x double>
ret <vscale x 2 x double> %bc
}
-
-define <vscale x 16 x i8> @bitcast_bfloat_to_i8(<vscale x 8 x bfloat> %v) #0 {
-; CHECK-LABEL: bitcast_bfloat_to_i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 16 x i8>
- ret <vscale x 16 x i8> %bc
-}
-
-define <vscale x 8 x i16> @bitcast_bfloat_to_i16(<vscale x 8 x bfloat> %v) #0 {
-; CHECK-LABEL: bitcast_bfloat_to_i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 8 x i16>
- ret <vscale x 8 x i16> %bc
-}
-
-define <vscale x 4 x i32> @bitcast_bfloat_to_i32(<vscale x 8 x bfloat> %v) #0 {
-; CHECK-LABEL: bitcast_bfloat_to_i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 4 x i32>
- ret <vscale x 4 x i32> %bc
-}
-
-define <vscale x 2 x i64> @bitcast_bfloat_to_i64(<vscale x 8 x bfloat> %v) #0 {
-; CHECK-LABEL: bitcast_bfloat_to_i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 2 x i64>
- ret <vscale x 2 x i64> %bc
-}
-
-define <vscale x 8 x half> @bitcast_bfloat_to_half(<vscale x 8 x bfloat> %v) #0 {
-; CHECK-LABEL: bitcast_bfloat_to_half:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 8 x half>
- ret <vscale x 8 x half> %bc
-}
-
-define <vscale x 4 x float> @bitcast_bfloat_to_float(<vscale x 8 x bfloat> %v) #0 {
-; CHECK-LABEL: bitcast_bfloat_to_float:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 4 x float>
- ret <vscale x 4 x float> %bc
-}
-
-define <vscale x 2 x double> @bitcast_bfloat_to_double(<vscale x 8 x bfloat> %v) #0 {
-; CHECK-LABEL: bitcast_bfloat_to_double:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 2 x double>
- ret <vscale x 2 x double> %bc
-}
-
-define <vscale x 8 x bfloat> @bitcast_i8_to_bfloat(<vscale x 16 x i8> %v) #0 {
-; CHECK-LABEL: bitcast_i8_to_bfloat:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 16 x i8> %v to <vscale x 8 x bfloat>
- ret <vscale x 8 x bfloat> %bc
-}
-
-define <vscale x 8 x bfloat> @bitcast_i16_to_bfloat(<vscale x 8 x i16> %v) #0 {
-; CHECK-LABEL: bitcast_i16_to_bfloat:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 8 x i16> %v to <vscale x 8 x bfloat>
- ret <vscale x 8 x bfloat> %bc
-}
-
-define <vscale x 8 x bfloat> @bitcast_i32_to_bfloat(<vscale x 4 x i32> %v) #0 {
-; CHECK-LABEL: bitcast_i32_to_bfloat:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 4 x i32> %v to <vscale x 8 x bfloat>
- ret <vscale x 8 x bfloat> %bc
-}
-
-define <vscale x 8 x bfloat> @bitcast_i64_to_bfloat(<vscale x 2 x i64> %v) #0 {
-; CHECK-LABEL: bitcast_i64_to_bfloat:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 2 x i64> %v to <vscale x 8 x bfloat>
- ret <vscale x 8 x bfloat> %bc
-}
-
-define <vscale x 8 x bfloat> @bitcast_half_to_bfloat(<vscale x 8 x half> %v) #0 {
-; CHECK-LABEL: bitcast_half_to_bfloat:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 8 x half> %v to <vscale x 8 x bfloat>
- ret <vscale x 8 x bfloat> %bc
-}
-
-define <vscale x 8 x bfloat> @bitcast_float_to_bfloat(<vscale x 4 x float> %v) #0 {
-; CHECK-LABEL: bitcast_float_to_bfloat:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 4 x float> %v to <vscale x 8 x bfloat>
- ret <vscale x 8 x bfloat> %bc
-}
-
-define <vscale x 8 x bfloat> @bitcast_double_to_bfloat(<vscale x 2 x double> %v) #0 {
-; CHECK-LABEL: bitcast_double_to_bfloat:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
- %bc = bitcast <vscale x 2 x double> %v to <vscale x 8 x bfloat>
- ret <vscale x 8 x bfloat> %bc
-}
-
-; +bf16 is required for the bfloat version.
-attributes #0 = { "target-features"="+sve,+bf16" }
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