[PATCH] D82483: [SVE] Code generation for fixed length vector adds.

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14897
+    Operands.push_back(V);
+  }
+
----------------
Could we modify the assert to remove the branch?

```
assert(isa<CondCodeSDNode>(V) || V.getValueType().isScalableVector() &&
           "Only scalable vectors are supported!");
```

Same with the code above too.


================
Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:1618
+  def : SVE_3_Op_Pat_SelZero<nxv2f64, int_op, nxv2i1, nxv2f64, nxv2f64, !cast<Pseudo>(NAME # _ZERO_D)>;
 }
 
----------------
Is having both ir_op and int_op problematic going forward? E.g. how to match an intrinsic with an undef merge.

X86 solves a similar problem with the tables in `lib/Target/X86/X86IntrinsicsInfo.h`. That might be something to consider long term. I'm not sure if it's a great fit though.

I don't think this needs to be changed now, but something to consider...



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  https://reviews.llvm.org/D82483/new/

https://reviews.llvm.org/D82483