[PATCH] D76883: [AMDGPU] Implement CFI for CSR spills

[Venkata Ramanaiah Nalamothu via Phabricator via llvm-commits]

RamNalamothu updated this revision to Diff 273684.
RamNalamothu added a comment.

Rebase and update get{S,V}GPRSpillSaveOpcode (SIInstrInfo.cpp) as
per https://reviews.llvm.org/rG46579471fd2b9c00ba982325f53f30192cc5797f


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76883/new/

https://reviews.llvm.org/D76883

Files:
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
  llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
  llvm/test/CodeGen/AMDGPU/debug-frame.ll
  llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
  llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir

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