[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

[Anil Mahmud via Phabricator via llvm-commits]

anil9 added inline comments.


================
Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:17
+unsigned int uia, *uiap;
+signed int *ia;
+signed short *sia;
----------------
nit: It seems that most pull requests follow an ordering like first signed declaration and then unsigned, declaration, this one follows too , except the above two lines.  And should the above declarations of chars, be along with these lines ?


================
Comment at: llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll:56
+
+; CHECK: lxvrdx
+; Function Attrs: norecurse nounwind readonly
----------------
I am not too familiar with the builtins but I never saw a check outside of the two braces in the test cases before,  is it not posible to include it inside the test cases ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82502/new/

https://reviews.llvm.org/D82502