[PATCH] D82593: Cleanup CallConvLower.cpp

[Seija Kijin via Phabricator via llvm-commits]

pi1024e created this revision.
pi1024e added reviewers: llvm.org, MaskRay.
Herald added subscribers: llvm-commits, kristof.beyls.
Herald added a project: LLVM.
pi1024e updated this revision to Diff 273488.

The CallConvLower code has a lot of jumps and incongruity in respect to the code's behavior despite there being functions that have identical behavior. For readability, and to highlight this, I refactored this file to better reflect that.

Not to mention, we do not need to assign to HaveRegParm until we go into the do-while loop.


https://reviews.llvm.org/D82593

Files:
  lib/CodeGen/CallingConvLower.cpp


Index: lib/CodeGen/CallingConvLower.cpp
===================================================================
--- lib/CodeGen/CallingConvLower.cpp
+++ lib/CodeGen/CallingConvLower.cpp
@@ -189,9 +189,7 @@
     return true; // Assume -msse-regparm might be in effect.
   if (!VT.isInteger())
     return false;
-  if (CC == CallingConv::X86_VectorCall || CC == CallingConv::X86_FastCall)
-    return true;
-  return false;
+  return (CC == CallingConv::X86_VectorCall || CC == CallingConv::X86_FastCall);
 }
 
 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs,
@@ -207,8 +205,8 @@
 
   // Allocate something of this value type repeatedly until we get assigned a
   // location in memory.
-  bool HaveRegParm = true;
-  while (HaveRegParm) {
+  bool HaveRegParm;
+  do {
     if (Fn(0, VT, VT, CCValAssign::Full, Flags, *this)) {
 #ifndef NDEBUG
       dbgs() << "Call has unhandled type " << EVT(VT).getEVTString()
@@ -217,7 +215,7 @@
       llvm_unreachable(nullptr);
     }
     HaveRegParm = Locs.back().isRegLoc();
-  }
+  } while (HaveRegParm);
 
   // Copy all the registers from the value locations we added.
   assert(NumLocs < Locs.size() && "CC assignment failed to add location");
@@ -248,7 +246,7 @@
     const TargetLowering *TL = MF.getSubtarget().getTargetLowering();
     const TargetRegisterClass *RC = TL->getRegClassFor(RegVT);
     for (MCPhysReg PReg : RemainingRegs) {
-      unsigned VReg = MF.addLiveIn(PReg, RC);
+      Register VReg = MF.addLiveIn(PReg, RC);
       Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT));
     }
   }


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