[PATCH] D82570: [ARM] Allow the fabs intrinsic to be tail predicated

[Sam Tebbs via Phabricator via llvm-commits]

samtebbs created this revision.
samtebbs added reviewers: samparker, SjoerdMeijer, dmgreen, olista01, simon_tatham, t.p.northover.
samtebbs added a project: LLVM.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
samtebbs updated this revision to Diff 273394.

This patch stops the fabs intrinsic from blocking tail predication.


https://reviews.llvm.org/D82570

Files:
  llvm/lib/Target/ARM/MVETailPredication.cpp
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-fabs.ll


Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-fabs.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-fabs.ll
@@ -0,0 +1,67 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs -disable-mve-tail-predication=false -o - %s | FileCheck %s
+define arm_aapcs_vfpcc void @fabs(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %blockSize) #0 {
+; CHECK-LABEL: foo:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r7, lr}
+; CHECK-NEXT:    push {r7, lr}
+; CHECK-NEXT:    .setfp r7, sp
+; CHECK-NEXT:    mov r7, sp
+; CHECK-NEXT:    cmp r2, #0
+; CHECK-NEXT:    it eq
+; CHECK-NEXT:    popeq {r7, pc}
+; CHECK-NEXT:    dlstp.32 lr, r2
+; CHECK-NEXT:    .p2align 2
+; CHECK-NEXT:  .LBB0_1: @ %vector.body
+; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    vldrw.u32 q0, [r0], #16
+; CHECK-NEXT:    vabs.f32 q0, q0
+; CHECK-NEXT:    vstrw.32 q0, [r1], #16
+; CHECK-NEXT:    letp lr, .LBB0_1
+; CHECK-NEXT:  @ %bb.2: @ %while.end
+; CHECK-NEXT:    pop {r7, pc}
+entry:
+  %cmp3 = icmp eq i32 %blockSize, 0
+  br i1 %cmp3, label %while.end, label %vector.ph
+
+vector.ph:                                        ; preds = %entry
+  %n.rnd.up = add i32 %blockSize, 3
+  %n.vec = and i32 %n.rnd.up, -4
+  %trip.count.minus.1 = add i32 %blockSize, -1
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %vector.ph
+  %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+  %next.gep = getelementptr float, float* %pDst, i32 %index
+  %next.gep13 = getelementptr float, float* %pSrcA, i32 %index
+  %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %trip.count.minus.1)
+  %0 = bitcast float* %next.gep13 to <4 x float>*
+  %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef)
+  %1 = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %wide.masked.load)
+  %2 = bitcast float* %next.gep to <4 x float>*
+  call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask)
+  %index.next = add i32 %index, 4
+  %3 = icmp eq i32 %index.next, %n.vec
+  br i1 %3, label %while.end, label %vector.body
+
+while.end:                                        ; preds = %vector.body, %entry
+  ret void
+}
+
+; Function Attrs: nosync nounwind readnone willreturn
+declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) #1
+
+; Function Attrs: argmemonly nounwind readonly willreturn
+declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) #2
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #3
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>) #4
+
+attributes #0 = { nofree nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-dotprod,-fp16fml,-hwdiv-arm,-i8mm,-sb,-sha2" "unsafe-fp-math"="true" "use-soft-float"="false" }
+attributes #1 = { nosync nounwind readnone willreturn }
+attributes #2 = { argmemonly nounwind readonly willreturn }
+attributes #3 = { nounwind readnone speculatable willreturn }
+attributes #4 = { argmemonly nounwind willreturn }
Index: llvm/lib/Target/ARM/MVETailPredication.cpp
===================================================================
--- llvm/lib/Target/ARM/MVETailPredication.cpp
+++ llvm/lib/Target/ARM/MVETailPredication.cpp
@@ -363,6 +363,7 @@
           case Intrinsic::round:
           case Intrinsic::floor:
           case Intrinsic::ceil:
+          case Intrinsic::fabs:
             continue;
           default:
             break;


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