[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai marked an inline comment as done.
HsiangKai added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56
+def NoConstraint : RISCVVConstraint<0>;
+def WidenV       : RISCVVConstraint<1>;
+def WidenW       : RISCVVConstraint<2>;
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evandro wrote:
> HsiangKai wrote:
> > evandro wrote:
> > > Methinks that these constraints `WidenV`, `WidenW`, `WidenCvt`, should be split up by their components.  IOW, into `Widen`, `Wide` (input), `Cvt`.  This way, it's easier to test for specific constraints.
> > Do you mean
> > 
> > WidenV = Widen;
> > WidenW = Widen | WideInput;
> > WidenCvt = Widen | Cvt;
> Yes.
Got it. I will improve it based on v0.9 implementation.


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