[PATCH] D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions

[Paolo Savini via Phabricator via llvm-commits]

PaoloS marked 4 inline comments as done.
PaoloS added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rv32Zbb.ll:41
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    beqz a0, .LBB2_2
+; RV32IB-NEXT:  # %bb.1: # %cond.false
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asb wrote:
> clz on a zero is a well defined operation that will return XLEN. So shouldn't this just lower to clz and ret?
I agree, unfortunately the code gets split into multiple basic blocks before the selection and just the block with the condition a0 != 0 has the ctlz operation in it. Since I can focus on one block per time when pattern matching that's what I could do from the backend.
I based the pattern matching of clz on the llvm instrinc llvm.ctlz.i32 that already relies on its own idiom recognition in the middle end. A solution could be to turn off the intrinsics and try to pattern match it directly from the backend, maybe we could semplify it. But the scope is limited.


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Comment at: llvm/test/CodeGen/RISCV/rv32Zbb.ll:61
+; RV32IB-NEXT:  # %bb.1: # %cond.false
+; RV32IB-NEXT:    ctz a0, a0
+; RV32IB-NEXT:    ret
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asb wrote:
> Same comment as for clz above
Same as above


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  https://reviews.llvm.org/D79870/new/

https://reviews.llvm.org/D79870