[llvm] bc7eb90 - MachineScheduler.h - reduce AliasAnalysis.h include to forward declaration. NFC.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-06-25T11:40:44+01:00
New Revision: bc7eb9010f4163973571871b14a943c377d1b4f3

URL: https://github.com/llvm/llvm-project/commit/bc7eb9010f4163973571871b14a943c377d1b4f3
DIFF: https://github.com/llvm/llvm-project/commit/bc7eb9010f4163973571871b14a943c377d1b4f3.diff

LOG: MachineScheduler.h - reduce AliasAnalysis.h include to forward declaration. NFC.

Replace legacy AliasAnalysis typedef with AAResults where necessary.

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/MachineScheduler.h

Removed: 
    


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diff  --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index 87612902b42d..a7edaaa90673 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -80,7 +80,6 @@
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Twine.h"
-#include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachinePassRegistry.h"
 #include "llvm/CodeGen/RegisterPressure.h"
@@ -102,6 +101,7 @@ extern cl::opt<bool> ForceTopDown;
 extern cl::opt<bool> ForceBottomUp;
 extern cl::opt<bool> VerifyScheduling;
 
+class AAResults;
 class LiveIntervals;
 class MachineDominatorTree;
 class MachineFunction;
@@ -121,7 +121,7 @@ struct MachineSchedContext {
   const MachineLoopInfo *MLI = nullptr;
   const MachineDominatorTree *MDT = nullptr;
   const TargetPassConfig *PassConfig = nullptr;
-  AliasAnalysis *AA = nullptr;
+  AAResults *AA = nullptr;
   LiveIntervals *LIS = nullptr;
 
   RegisterClassInfo *RegClassInfo;
@@ -264,7 +264,7 @@ class MachineSchedStrategy {
 /// PreRA and PostRA MachineScheduler.
 class ScheduleDAGMI : public ScheduleDAGInstrs {
 protected:
-  AliasAnalysis *AA;
+  AAResults *AA;
   LiveIntervals *LIS;
   std::unique_ptr<MachineSchedStrategy> SchedImpl;