[PATCH] D82483: [SVE] Code generation for fixed length vector adds.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm created this revision.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.
paulwalker-arm added reviewers: sdesmalen, david-arm.
paulwalker-arm added a comment.
paulwalker-arm updated this revision to Diff 273098.

I've deviated from the base fixed length support to create this patch that adds the base work that's likely common to many of the arithmetic and logical operations.  I went with refactoring LowerToPredicatedOp as it's likely to be used in all the same places as those required for fixed length types.

I've probably gone overboard with the tests but I figure doing so for just the adds gives us enough coverage so that people adding support for similar operations only require minimal tests.  Perhaps this matches what I've done for element types like double or perhaps we can just add tests for a single vector length (e.g. 512bit).

NOTE: Patch requires D82466 <https://reviews.llvm.org/D82466> for sve-fixed-length-int-arith.ll to pass.




paulwalker-arm added a comment.

Fixed a couple of lines missing -DAG.


Teach LowerToPredicatedOp to lower fixed length vector operations.

Add AArch64ISD nodes and isel patterns for predicated integer
and floating point adds.

Together this enables SVE code generation for fixed length vector adds.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82483

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll

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