[PATCH] D82463: [AMDGPU] Spill more than wavesize CSR SGPRs

[Saiyedul Islam via Phabricator via llvm-commits]

saiislam created this revision.
saiislam added reviewers: arsenm, sameerds, rampitec, cdevadas.
Herald added subscribers: llvm-commits, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, qcolombet.
Herald added a project: LLVM.

In case of more than wavesize CSR SGPR spills, lanes of reserved VGPR were getting
overwritten due to wrap around.

Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and when one
of the two conditions is true:

1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet reserved.
2. All spill lanes of reserved VGPR(s) are full and another spill lane is required.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82463

Files:
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll


Index: llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
@@ -0,0 +1,24 @@
+; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -enable-var-scope %s
+
+; CHECK-LABEL: {{^}}spill_more_than_wavesize_csr_sgprs:
+; CHECK:        v_writelane_b32 v1, s98, 63
+; CHECK-NEXT:   v_writelane_b32 v2, s99, 0
+; CHECK:        v_readlane_b32 s99, v2, 0
+; CHECK-NEXT:   v_readlane_b32 s98, v1, 63
+
+define void @spill_more_than_wavesize_csr_sgprs() {
+  %alloca = alloca i32, align 4, addrspace(5)
+  store volatile i32 0, i32 addrspace(5)* %alloca
+  call void asm sideeffect "",
+   "~{s35},~{s36},~{s37},~{s38},~{s39},~{s40},~{s41},~{s42}
+   ,~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49},~{s50}
+   ,~{s51},~{s52},~{s53},~{s54},~{s55},~{s56},~{s57},~{s58}
+   ,~{s59},~{s60},~{s61},~{s62},~{s63},~{s64},~{s65},~{s66}
+   ,~{s67},~{s68},~{s69},~{s70},~{s71},~{s72},~{s73},~{s74}
+   ,~{s75},~{s76},~{s77},~{s78},~{s79},~{s80},~{s81},~{s82}
+   ,~{s83},~{s84},~{s85},~{s86},~{s87},~{s88},~{s89},~{s90}
+   ,~{s91},~{s92},~{s93},~{s94},~{s95},~{s96},~{s97},~{s98}
+   ,~{s99},~{s100},~{s101},~{s102}"()
+  ret void
+}
+
Index: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -303,7 +303,15 @@
     Register LaneVGPR;
     unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
 
-    if (VGPRIndex == 0 && !FuncInfo->VGPRReservedForSGPRSpill) {
+    // Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and
+    // when one of the two conditions is true:
+    // 1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet
+    // reserved.
+    // 2. All spill lanes of reserved VGPR(s) are full and another spill lane is
+    // required.
+    if (VGPRIndex == 0 && (!FuncInfo->VGPRReservedForSGPRSpill ||
+                           NumVGPRSpillLanes >= WaveSize)) {
+
       LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
       if (LaneVGPR == AMDGPU::NoRegister) {
         // We have no VGPRs left for spilling SGPRs. Reset because we will not


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