[PATCH] D82451: [AMDGPU] Fix DPP Combiner:

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin created this revision.
vpykhtin added reviewers: arsenm, rampitec, foad.
Herald added subscribers: llvm-commits, kerbowa, kbarton, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, nemanjai, kzhuravl.
Herald added a project: LLVM.

1. skip multiple per instruction DPP register usage.
2. don't combine when DPP register is used as part of superreg/supersubreg.

I had to refactor the code to fix the first issue, so that the check for
multiple uses of DPP register can be done for all uses. In the process
I discovered that the combiner can try to combine DPP registers that
are part of superreg (REG_SEQUENCE) and aren't used as independent lanes.

execMayBeModifiedBeforeAnyUse is now called once for all uses. Number of
uses is constrained by the caller.

I removed code patching REG_SEQUENCE but instead stopped deleting original
DPP mov instruction, it will be deleted in the DCE.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82451

Files:
  llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/test/CodeGen/AMDGPU/dpp_combine.mir

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