[PATCH] D82298: [AArch64][SVE] Add bfloat16 support to load intrinsics
Sander de Smalen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 24 02:40:13 PDT 2020
sdesmalen accepted this revision.
sdesmalen added a comment.
LGTM
================
Comment at: clang/include/clang/Basic/arm_sve.td:275
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
+ def SVLD1_BF : MInst<"svld1[_{2}]", "dPc", "b", [IsLoad], MemEltTyDefault, "aarch64_sve_ld1">;
+ def SVLD1_VNUM_BF : MInst<"svld1_vnum[_{2}]", "dPcl", "b", [IsLoad], MemEltTyDefault, "aarch64_sve_ld1">;
----------------
micro nit: doesn't match column indentation of the code around it.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82298/new/
https://reviews.llvm.org/D82298
More information about the llvm-commits
mailing list