[PATCH] D68667: [SLP] respect target register width for GEP vectorization (PR43578)

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

(there are also a bunch of slightly odd cost-model decision I ran into (e.g. all extracts on AArch64 for indices > 0 have a cost of 3 for some reason...); I'll prepare some patches for some of the issue I encountered when I have a bit more time)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68667/new/

https://reviews.llvm.org/D68667