[llvm] d604cc6 - [ARM] Mark more integer instructions as not having side effects.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 23 14:47:02 PDT 2020
Author: David Green
Date: 2020-06-23T22:45:51+01:00
New Revision: d604cc6e9a41aa6cf1759b8c58c8d02e5c87dda2
URL: https://github.com/llvm/llvm-project/commit/d604cc6e9a41aa6cf1759b8c58c8d02e5c87dda2
DIFF: https://github.com/llvm/llvm-project/commit/d604cc6e9a41aa6cf1759b8c58c8d02e5c87dda2.diff
LOG: [ARM] Mark more integer instructions as not having side effects.
LDRD and STRD along with UBFX and SBFX are selected from DAGToDAG
transforms, so do not have tblgen patterns. They don't get marked as
having side effects so cannot be scheduled as efficiently as you would
like.
This specifically marks then as not having side effects.
Differential Revision: https://reviews.llvm.org/D82358
Added:
Modified:
llvm/lib/Target/ARM/ARMInstrThumb2.td
llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
llvm/test/tools/llvm-mca/ARM/m4-int.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index e2235b1c2501..7137e8ee66b8 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -1748,7 +1748,7 @@ def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
// ldrd / strd pre / post variants
-let mayLoad = 1 in
+let mayLoad = 1, hasSideEffects = 0 in
def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
(ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
"ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
@@ -1756,13 +1756,13 @@ def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
let DecoderMethod = "DecodeT2LDRDPreInstruction";
}
-let mayLoad = 1 in
+let mayLoad = 1, hasSideEffects = 0 in
def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
(ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
"$addr.base = $wb", []>, Sched<[WriteLd]>;
-let mayStore = 1 in
+let mayStore = 1, hasSideEffects = 0 in
def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
(ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
@@ -1770,7 +1770,7 @@ def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
let DecoderMethod = "DecodeT2STRDPreInstruction";
}
-let mayStore = 1 in
+let mayStore = 1, hasSideEffects = 0 in
def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
(ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
t2am_imm8s4_offset:$imm),
@@ -2765,6 +2765,8 @@ def t2SBFX: T2TwoRegBitFI<
let Inst{25} = 1;
let Inst{24-20} = 0b10100;
let Inst{15} = 0;
+
+ let hasSideEffects = 0;
}
def t2UBFX: T2TwoRegBitFI<
@@ -2774,6 +2776,8 @@ def t2UBFX: T2TwoRegBitFI<
let Inst{25} = 1;
let Inst{24-20} = 0b11100;
let Inst{15} = 0;
+
+ let hasSideEffects = 0;
}
// A8.8.247 UDF - Undefined (Encoding T2)
diff --git a/llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll b/llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
index 066c0957f526..795e218d7fe2 100644
--- a/llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
@@ -913,11 +913,11 @@ define void @foo_v4f32_v4f16(<4 x float> *%dest, <4 x i16> *%mask, <4 x half> *%
; CHECK-NEXT: vmov.16 q1[3], r1
; CHECK-NEXT: .LBB18_9: @ %else8
; CHECK-NEXT: vmrs r2, p0
+; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vmovx.f16 s0, s5
-; CHECK-NEXT: vcvtb.f32.f16 s3, s0
; CHECK-NEXT: vmovx.f16 s8, s4
+; CHECK-NEXT: vcvtb.f32.f16 s3, s0
; CHECK-NEXT: vcvtb.f32.f16 s2, s5
-; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vcvtb.f32.f16 s1, s8
; CHECK-NEXT: vcvtb.f32.f16 s0, s4
; CHECK-NEXT: and r3, r2, #1
@@ -1041,11 +1041,11 @@ define void @foo_v4f32_v4f16_unaligned(<4 x float> *%dest, <4 x i16> *%mask, <4
; CHECK-NEXT: vmov.16 q1[3], r1
; CHECK-NEXT: .LBB19_9: @ %else8
; CHECK-NEXT: vmrs r2, p0
+; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vmovx.f16 s0, s5
-; CHECK-NEXT: vcvtb.f32.f16 s3, s0
; CHECK-NEXT: vmovx.f16 s8, s4
+; CHECK-NEXT: vcvtb.f32.f16 s3, s0
; CHECK-NEXT: vcvtb.f32.f16 s2, s5
-; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vcvtb.f32.f16 s1, s8
; CHECK-NEXT: vcvtb.f32.f16 s0, s4
; CHECK-NEXT: and r3, r2, #1
diff --git a/llvm/test/tools/llvm-mca/ARM/m4-int.s b/llvm/test/tools/llvm-mca/ARM/m4-int.s
index 3dedacdeb2a3..b46f731f0793 100644
--- a/llvm/test/tools/llvm-mca/ARM/m4-int.s
+++ b/llvm/test/tools/llvm-mca/ARM/m4-int.s
@@ -562,8 +562,8 @@ yield
# CHECK-NEXT: 1 2 1.00 U ldrbt r0, [r1, #1]
# CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1]
# CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1, #-4]
-# CHECK-NEXT: 1 2 1.00 * U ldrd r0, r2, [r1], #4
-# CHECK-NEXT: 1 2 1.00 * U ldrd r0, r2, [r1, #4]!
+# CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1], #4
+# CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1, #4]!
# CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, next
# CHECK-NEXT: 1 2 1.00 * * U ldrex r0, [r1]
# CHECK-NEXT: 1 2 1.00 * * U ldrex r0, [r1, #4]
@@ -700,7 +700,7 @@ yield
# CHECK-NEXT: 1 1 1.00 sbcs.w r0, r1, r2
# CHECK-NEXT: 1 1 1.00 sbc.w r0, r1, r2, lsl #1
# CHECK-NEXT: 1 1 1.00 sbcs.w r0, r1, r2, lsl #1
-# CHECK-NEXT: 1 1 1.00 U sbfx r0, r1, #1, #2
+# CHECK-NEXT: 1 1 1.00 sbfx r0, r1, #1, #2
# CHECK-NEXT: 1 2 1.00 sdiv r0, r1, r2
# CHECK-NEXT: 1 1 1.00 * sel r0, r1, r2
# CHECK-NEXT: 1 1 1.00 * * U sev
@@ -778,8 +778,8 @@ yield
# CHECK-NEXT: 1 1 1.00 * strb.w r0, [r1, r2, lsl #1]
# CHECK-NEXT: 1 1 1.00 U strbt r0, [r1, #1]
# CHECK-NEXT: 1 1 1.00 * strd r0, r1, [r2, #4]
-# CHECK-NEXT: 1 1 1.00 * U strd r0, r1, [r2], #4
-# CHECK-NEXT: 1 1 1.00 * U strd r0, r1, [r2, #4]!
+# CHECK-NEXT: 1 1 1.00 * strd r0, r1, [r2], #4
+# CHECK-NEXT: 1 1 1.00 * strd r0, r1, [r2, #4]!
# CHECK-NEXT: 1 1 1.00 * * U strex r0, r1, [r2]
# CHECK-NEXT: 1 1 1.00 * * U strex r0, r1, [r2, #4]
# CHECK-NEXT: 1 1 1.00 * * U strexb r0, r1, [r2]
@@ -839,7 +839,7 @@ yield
# CHECK-NEXT: 1 1 1.00 * * U uadd16 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 * * U uadd8 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 * * U uasx r0, r1, r2
-# CHECK-NEXT: 1 1 1.00 U ubfx r0, r1, #1, #2
+# CHECK-NEXT: 1 1 1.00 ubfx r0, r1, #1, #2
# CHECK-NEXT: 1 2 1.00 udiv r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uhadd16 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uhadd8 r0, r1, r2
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