[PATCH] D81416: [LV][SLP] Interleave to expose ILP for small loops with scalar reductions.

[Aaron H Liu via Phabricator via llvm-commits]

AaronLiu added a comment.

In D81416#2108976 <https://reviews.llvm.org/D81416#2108976>, @spatel wrote:

> In D81416#2099655 <https://reviews.llvm.org/D81416#2099655>, @AaronLiu wrote:
>
> > I add a test: llvm/test/Transforms/PhaseOrdering/interleave_LV_SLP.ll
> >  Please let me know whether that is what you wanted.
>
>
> Thanks - that was the start of what I requested, but not complete. I've added the test here using auto-generated CHECK lines that show baseline (without this patch) results:
>  rGdf79443 <https://reviews.llvm.org/rGdf794431e0a36d7d4fda685710714e913277f22f>
>
> Please rebase and update that file using the script at llvm/utils/update_test_checks.py.
>  I don't think we need to duplicate the test in the SLP folder now that we have coverage for this example in PhaseOrdering, but if you think that is still useful, that can be added independently of this patch.


Thanks - I rebase and update PhaseOrdering/interleave_LV_SLP.ll using auto-generated CHECK lines that show baseline (with this patch) results.
I think all the four testcases are related to this patch, and I prefer to keep the testcase in this patch. The four testcases all serve different purposes:

- PhaseOrdering/interleave_LV_SLP.ll shows that with the option in this patch on, instructions were vectorized. But which vectorizer make it work? We cannot tell.
- Vectorize/LoopVectorize.cpp tells us that LV cannot vectorize the code, but interleave the instructions to expose ILP.
- SLPVectorizer/PowerPC/interleave_SLP.ll demonstrates that after interleaving by LV, then SLP captures the opportunities and vectorize the instructions.
- The one you added in PhaseOrdering/interleave-vectorization.ll show that without this patch(equivalently with the option in this patch off), the same testcase both LV and SLP cannot vectorize the instructions.


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