[llvm] f09ef03 - [PowerPC][NFC] Add tests for variadic functions on PPC64
Kai Luo via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 23 02:20:31 PDT 2020
Author: Kai Luo
Date: 2020-06-23T09:20:04Z
New Revision: f09ef03e1c52bd09bff2d5d3720fb3c9ae0e8a23
URL: https://github.com/llvm/llvm-project/commit/f09ef03e1c52bd09bff2d5d3720fb3c9ae0e8a23
DIFF: https://github.com/llvm/llvm-project/commit/f09ef03e1c52bd09bff2d5d3720fb3c9ae0e8a23.diff
LOG: [PowerPC][NFC] Add tests for variadic functions on PPC64
Added:
llvm/test/CodeGen/PowerPC/ppc64-varargs.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-varargs.ll b/llvm/test/CodeGen/PowerPC/ppc64-varargs.ll
new file mode 100644
index 000000000000..56816aee6704
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ppc64-varargs.ll
@@ -0,0 +1,76 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -mtriple=powerpc64 \
+; RUN: < %s | FileCheck --check-prefix=BE %s
+; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -mtriple=powerpc64le \
+; RUN: < %s | FileCheck --check-prefix=LE %s
+
+define i32 @f(...) nounwind {
+; BE-LABEL: f:
+; BE: # %bb.0: # %entry
+; BE-NEXT: mr r11, r3
+; BE-NEXT: li r3, 0
+; BE-NEXT: std r11, 48(r1)
+; BE-NEXT: std r4, 56(r1)
+; BE-NEXT: std r5, 64(r1)
+; BE-NEXT: std r6, 72(r1)
+; BE-NEXT: std r7, 80(r1)
+; BE-NEXT: std r8, 88(r1)
+; BE-NEXT: std r9, 96(r1)
+; BE-NEXT: std r10, 104(r1)
+; BE-NEXT: blr
+;
+; LE-LABEL: f:
+; LE: # %bb.0: # %entry
+; LE-NEXT: std r3, 32(r1)
+; LE-NEXT: li r3, 0
+; LE-NEXT: std r4, 40(r1)
+; LE-NEXT: std r5, 48(r1)
+; LE-NEXT: std r6, 56(r1)
+; LE-NEXT: std r7, 64(r1)
+; LE-NEXT: std r8, 72(r1)
+; LE-NEXT: std r9, 80(r1)
+; LE-NEXT: std r10, 88(r1)
+; LE-NEXT: blr
+entry:
+ ret i32 0
+}
+
+define i32 @f1(...) nounwind {
+; BE-LABEL: f1:
+; BE: # %bb.0: # %entry
+; BE-NEXT: mr r11, r3
+; BE-NEXT: addi r12, r1, 48
+; BE-NEXT: li r3, 0
+; BE-NEXT: std r11, 48(r1)
+; BE-NEXT: std r4, 56(r1)
+; BE-NEXT: std r5, 64(r1)
+; BE-NEXT: std r6, 72(r1)
+; BE-NEXT: std r7, 80(r1)
+; BE-NEXT: std r8, 88(r1)
+; BE-NEXT: std r9, 96(r1)
+; BE-NEXT: std r10, 104(r1)
+; BE-NEXT: std r12, -8(r1)
+; BE-NEXT: blr
+;
+; LE-LABEL: f1:
+; LE: # %bb.0: # %entry
+; LE-NEXT: std r3, 32(r1)
+; LE-NEXT: std r4, 40(r1)
+; LE-NEXT: addi r4, r1, 32
+; LE-NEXT: li r3, 0
+; LE-NEXT: std r5, 48(r1)
+; LE-NEXT: std r6, 56(r1)
+; LE-NEXT: std r7, 64(r1)
+; LE-NEXT: std r8, 72(r1)
+; LE-NEXT: std r9, 80(r1)
+; LE-NEXT: std r10, 88(r1)
+; LE-NEXT: std r4, -8(r1)
+; LE-NEXT: blr
+entry:
+ %va = alloca i8*, align 8
+ %va.cast = bitcast i8** %va to i8*
+ call void @llvm.va_start(i8* %va.cast)
+ ret i32 0
+}
+
+declare void @llvm.va_start(i8*) nounwind
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