[llvm] ce7a1dc - [AMDGPU] Generate test checks
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 22 08:08:53 PDT 2020
Author: Jay Foad
Date: 2020-06-22T16:08:40+01:00
New Revision: ce7a1dc4e90f17642d0d725a2026b233fff0b6b6
URL: https://github.com/llvm/llvm-project/commit/ce7a1dc4e90f17642d0d725a2026b233fff0b6b6
DIFF: https://github.com/llvm/llvm-project/commit/ce7a1dc4e90f17642d0d725a2026b233fff0b6b6.diff
LOG: [AMDGPU] Generate test checks
Added:
Modified:
llvm/test/CodeGen/AMDGPU/udivrem.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/udivrem.ll b/llvm/test/CodeGen/AMDGPU/udivrem.ll
index 326eda5296cf..f76174369cb4 100644
--- a/llvm/test/CodeGen/AMDGPU/udivrem.ll
+++ b/llvm/test/CodeGen/AMDGPU/udivrem.ll
@@ -1,57 +1,130 @@
-; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=SI --check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=SI --check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=EG --check-prefix=FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 %s
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck --check-prefix=GFX6 %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
-; FUNC-LABEL: {{^}}test_udivrem:
-; EG: RECIP_UINT
-; EG-DAG: MULHI
-; EG-DAG: MULLO_INT
-; EG-DAG: SUB_INT
-; EG: CNDE_INT
-; EG: MULHI
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG: CNDE_INT
-; EG: MULHI
-; EG: MULLO_INT
-; EG: SUB_INT
-; EG-DAG: SETGE_UINT
-; EG-DAG: SETGE_UINT
-; EG: AND_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-
-; SI: v_rcp_iflag_f32_e32 [[RCP:v[0-9]+]]
-; SI-DAG: v_mul_hi_u32 [[RCP_HI:v[0-9]+]], [[RCP]]
-; SI-DAG: v_mul_lo_u32 [[RCP_LO:v[0-9]+]], [[RCP]]
-; SI-DAG: v_sub_{{[iu]}}32_e32 [[NEG_RCP_LO:v[0-9]+]], vcc, 0, [[RCP_LO]]
-; SI: v_cmp_eq_u32_e64 [[CC1:s\[[0-9:]+\]]], 0, [[RCP_HI]]
-; SI: v_cndmask_b32_e64 [[CND1:v[0-9]+]], [[RCP_LO]], [[NEG_RCP_LO]], [[CC1]]
-; SI: v_mul_hi_u32 [[E:v[0-9]+]], [[CND1]], [[RCP]]
-; SI-DAG: v_add_{{[iu]}}32_e32 [[RCP_A_E:v[0-9]+]], vcc, [[E]], [[RCP]]
-; SI-DAG: v_subrev_{{[iu]}}32_e32 [[RCP_S_E:v[0-9]+]], vcc, [[E]], [[RCP]]
-; SI: v_cndmask_b32_e64 [[CND2:v[0-9]+]], [[RCP_S_E]], [[RCP_A_E]], [[CC1]]
-; SI: v_mul_hi_u32 [[Quotient:v[0-9]+]], [[CND2]],
-; SI: v_mul_lo_u32 [[Num_S_Remainder:v[0-9]+]], [[CND2]]
-; SI-DAG: v_add_{{[iu]}}32_e32 [[Quotient_A_One:v[0-9]+]], vcc, 1, [[Quotient]]
-; SI-DAG: v_sub_{{[iu]}}32_e32 [[Remainder:v[0-9]+]], vcc, {{[vs][0-9]+}}, [[Num_S_Remainder]]
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_subrev_{{[iu]}}32_e32 [[Quotient_S_One:v[0-9]+]],
-; SI-DAG: v_subrev_{{[iu]}}32_e32 [[Remainder_S_Den:v[0-9]+]],
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_{{[iu]}}32_e32 [[Remainder_A_Den:v[0-9]+]],
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-NOT: v_and_b32
-; SI: s_endpgm
define amdgpu_kernel void @test_udivrem(i32 addrspace(1)* %out0, [8 x i32], i32 addrspace(1)* %out1, [8 x i32], i32 %x, [8 x i32], i32 %y) {
+; R600-LABEL: test_udivrem:
+; R600: ; %bb.0:
+; R600-NEXT: ALU 27, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T3.X, 0
+; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T2.X, 1
+; R600-NEXT: CF_END
+; R600-NEXT: ALU clause starting at 4:
+; R600-NEXT: RECIP_UINT * T0.X, KC0[9].X,
+; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[9].X,
+; R600-NEXT: SUB_INT T0.W, 0.0, PS,
+; R600-NEXT: MULHI * T0.Z, T0.X, KC0[9].X,
+; R600-NEXT: CNDE_INT * T0.W, PS, PV.W, T0.Y,
+; R600-NEXT: MULHI * T0.Y, PV.W, T0.X,
+; R600-NEXT: ADD_INT T0.W, T0.X, PS,
+; R600-NEXT: SUB_INT * T1.W, T0.X, PS,
+; R600-NEXT: CNDE_INT * T0.W, T0.Z, PV.W, PS,
+; R600-NEXT: MULHI * T0.X, PV.W, KC0[6].W,
+; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[9].X,
+; R600-NEXT: SUB_INT * T0.W, KC0[6].W, PS,
+; R600-NEXT: SETGE_UINT T1.W, PV.W, KC0[9].X,
+; R600-NEXT: SETGE_UINT * T2.W, KC0[6].W, T0.Y,
+; R600-NEXT: AND_INT T1.W, PV.W, PS,
+; R600-NEXT: SUB_INT * T3.W, T0.W, KC0[9].X,
+; R600-NEXT: CNDE_INT T3.W, PV.W, T0.W, PS,
+; R600-NEXT: ADD_INT * T0.W, T0.W, KC0[9].X,
+; R600-NEXT: CNDE_INT T1.X, T2.W, PS, PV.W,
+; R600-NEXT: ADD_INT T0.W, T0.X, 1,
+; R600-NEXT: LSHR * T2.X, KC0[4].Z, literal.x,
+; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; R600-NEXT: CNDE_INT T0.W, T1.W, T0.X, PV.W,
+; R600-NEXT: ADD_INT * T1.W, T0.X, literal.x,
+; R600-NEXT: -1(nan), 0(0.000000e+00)
+; R600-NEXT: CNDE_INT T0.X, T2.W, PS, PV.W,
+; R600-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
+; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX6-LABEL: test_udivrem:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dword s13, s[0:1], 0x26
+; GFX6-NEXT: s_load_dword s12, s[0:1], 0x1d
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x13
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s13
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, v0, s13
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, s13
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3]
+; GFX6-NEXT: v_mul_hi_u32 v1, v1, v0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v1, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3]
+; GFX6-NEXT: v_mul_hi_u32 v0, v0, s12
+; GFX6-NEXT: v_mul_lo_u32 v1, v0, s13
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, -1, v0
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s12, v1
+; GFX6-NEXT: v_cmp_ge_u32_e64 s[0:1], s12, v1
+; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v4
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s13, v4
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, s13, v4
+; GFX6-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v5, v1, s[0:1]
+; GFX6-NEXT: buffer_store_dword v0, off, s[8:11], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: test_udivrem:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dword s7, s[0:1], 0x98
+; GFX8-NEXT: s_load_dword s6, s[0:1], 0x74
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s7
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_lo_u32 v1, v0, s7
+; GFX8-NEXT: v_mul_hi_u32 v2, v0, s7
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 0, v1
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3]
+; GFX8-NEXT: v_mul_hi_u32 v1, v1, v0
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, v1, v0
+; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, v1, v0
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3]
+; GFX8-NEXT: v_mul_hi_u32 v2, v0, s6
+; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x4c
+; GFX8-NEXT: v_mul_lo_u32 v3, v2, s7
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v2
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, s6, v3
+; GFX8-NEXT: v_cmp_ge_u32_e64 s[0:1], s6, v3
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, -1, v2
+; GFX8-NEXT: v_cmp_le_u32_e64 s[2:3], s7, v6
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s7, v6
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, s7, v6
+; GFX8-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1]
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, v3, s[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
%result0 = udiv i32 %x, %y
store i32 %result0, i32 addrspace(1)* %out0
%result1 = urem i32 %x, %y
@@ -59,103 +132,168 @@ define amdgpu_kernel void @test_udivrem(i32 addrspace(1)* %out0, [8 x i32], i32
ret void
}
-; FUNC-LABEL: {{^}}test_udivrem_v2:
-; EG-DAG: RECIP_UINT
-; EG-DAG: MULHI
-; EG-DAG: MULLO_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: MULHI
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: MULHI
-; EG-DAG: MULLO_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SETGE_UINT
-; EG-DAG: SETGE_UINT
-; EG-DAG: AND_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: RECIP_UINT
-; EG-DAG: MULHI
-; EG-DAG: MULLO_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: MULHI
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: MULHI
-; EG-DAG: MULLO_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SETGE_UINT
-; EG-DAG: SETGE_UINT
-; EG-DAG: AND_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-
-; For SI, we used to have checks for the input and output registers
-; of the instructions, but these are way too fragile. The division for
-; the two vector elements can be intermixed which makes it impossible to
-; accurately check all the operands.
-; SI-DAG: v_rcp_iflag_f32_e32
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_mul_lo_u32
-; SI-DAG: v_sub_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_mul_lo_u32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_rcp_iflag_f32_e32
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_mul_lo_u32
-; SI-DAG: v_sub_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_mul_lo_u32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-NOT: v_and_b32
-; SI: s_endpgm
define amdgpu_kernel void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
+; R600-LABEL: test_udivrem_v2:
+; R600: ; %bb.0:
+; R600-NEXT: ALU 39, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+; R600-NEXT: ALU clause starting at 4:
+; R600-NEXT: RECIP_UINT * T0.X, KC0[3].Z,
+; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[3].Z,
+; R600-NEXT: RECIP_UINT * T0.Z, KC0[3].Y,
+; R600-NEXT: MULLO_INT * T0.W, PS, KC0[3].Y,
+; R600-NEXT: SUB_INT T1.W, 0.0, PS,
+; R600-NEXT: MULHI * T1.X, T0.Z, KC0[3].Y,
+; R600-NEXT: CNDE_INT T1.Z, PS, PV.W, T0.W,
+; R600-NEXT: SUB_INT T0.W, 0.0, T0.Y,
+; R600-NEXT: MULHI * T1.Y, T0.X, KC0[3].Z,
+; R600-NEXT: CNDE_INT T0.W, PS, PV.W, T0.Y,
+; R600-NEXT: MULHI * T0.Y, PV.Z, T0.Z,
+; R600-NEXT: ADD_INT T1.Z, T0.Z, PS,
+; R600-NEXT: SUB_INT T1.W, T0.Z, PS,
+; R600-NEXT: MULHI * T0.Y, PV.W, T0.X,
+; R600-NEXT: CNDE_INT T0.Z, T1.X, PV.Z, PV.W,
+; R600-NEXT: ADD_INT T0.W, T0.X, PS, BS:VEC_120/SCL_212
+; R600-NEXT: SUB_INT * T1.W, T0.X, PS,
+; R600-NEXT: CNDE_INT T0.W, T1.Y, PV.W, PS,
+; R600-NEXT: MULHI * T0.X, PV.Z, KC0[2].W,
+; R600-NEXT: MULHI * T0.Y, PV.W, KC0[3].X,
+; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[3].Z,
+; R600-NEXT: SUB_INT T0.W, KC0[3].X, PS,
+; R600-NEXT: MULLO_INT * T0.X, T0.X, KC0[3].Y,
+; R600-NEXT: SUB_INT T0.Z, KC0[2].W, PS,
+; R600-NEXT: SETGE_UINT * T1.W, PV.W, KC0[3].Z,
+; R600-NEXT: SETGE_UINT * T2.W, KC0[3].X, T0.Y,
+; R600-NEXT: AND_INT T0.Y, T1.W, PV.W,
+; R600-NEXT: SUB_INT T1.Z, T0.W, KC0[3].Z, BS:VEC_120/SCL_212
+; R600-NEXT: SETGE_UINT * T1.W, T0.Z, KC0[3].Y,
+; R600-NEXT: SETGE_UINT * T3.W, KC0[2].W, T0.X,
+; R600-NEXT: AND_INT T1.Y, T1.W, PV.W,
+; R600-NEXT: SUB_INT T2.Z, T0.Z, KC0[3].Y,
+; R600-NEXT: CNDE_INT T1.W, T0.Y, T0.W, T1.Z,
+; R600-NEXT: ADD_INT * T0.W, T0.W, KC0[3].Z,
+; R600-NEXT: CNDE_INT T0.Y, T2.W, PS, PV.W,
+; R600-NEXT: CNDE_INT T0.W, PV.Y, T0.Z, PV.Z,
+; R600-NEXT: ADD_INT * T1.W, T0.Z, KC0[3].Y,
+; R600-NEXT: CNDE_INT T0.X, T3.W, PS, PV.W,
+; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX6-LABEL: test_udivrem_v2:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s2, 0x4f800000
+; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NEXT: s_mov_b32 s10, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s6
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, s6
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0, v2
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
+; GFX6-NEXT: v_mul_hi_u32 v2, v2, v0
+; GFX6-NEXT: v_mul_lo_u32 v3, v1, s7
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v2, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT: v_mul_hi_u32 v2, v1, s7
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
+; GFX6-NEXT: v_mul_hi_u32 v0, v0, s4
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1]
+; GFX6-NEXT: v_mul_hi_u32 v2, v2, v1
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v2, v1
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
+; GFX6-NEXT: v_mul_hi_u32 v1, v1, s5
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v0
+; GFX6-NEXT: v_cmp_ge_u32_e64 s[0:1], s4, v0
+; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s6, v3
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s7
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, s6, v3
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s6, v3
+; GFX6-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s5, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[0:1]
+; GFX6-NEXT: v_cmp_ge_u32_e64 s[2:3], s5, v1
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v2
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, s7, v2
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s7, v2
+; GFX6-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[2:3]
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: test_udivrem_v2:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x2c
+; GFX8-NEXT: s_mov_b32 s2, 0x4f800000
+; GFX8-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s10
+; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s11
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX8-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX8-NEXT: v_mul_hi_u32 v2, v0, s10
+; GFX8-NEXT: v_mul_lo_u32 v3, v0, s10
+; GFX8-NEXT: v_mul_hi_u32 v4, v1, s11
+; GFX8-NEXT: v_mul_lo_u32 v5, v1, s11
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0, v3
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v6, s[2:3]
+; GFX8-NEXT: v_mul_hi_u32 v2, v2, v0
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 0, v5
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, v2, v0
+; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, v2, v0
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v5, v3, s[4:5]
+; GFX8-NEXT: v_mul_hi_u32 v2, v2, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[2:3]
+; GFX8-NEXT: v_mul_hi_u32 v0, v0, s8
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v1
+; GFX8-NEXT: v_subrev_u32_e32 v1, vcc, v2, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5]
+; GFX8-NEXT: v_mul_hi_u32 v1, v1, s9
+; GFX8-NEXT: v_mul_lo_u32 v0, v0, s10
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, s11
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s8, v0
+; GFX8-NEXT: v_cmp_ge_u32_e64 s[0:1], s8, v0
+; GFX8-NEXT: v_cmp_le_u32_e64 s[2:3], s10, v4
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, s10, v4
+; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s10, v4
+; GFX8-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s9, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[0:1]
+; GFX8-NEXT: v_cmp_ge_u32_e64 s[2:3], s9, v1
+; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v2
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, s11, v2
+; GFX8-NEXT: v_subrev_u32_e32 v1, vcc, s11, v2
+; GFX8-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[2:3]
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX8-NEXT: s_endpgm
%result0 = udiv <2 x i32> %x, %y
store <2 x i32> %result0, <2 x i32> addrspace(1)* %out
%result1 = urem <2 x i32> %x, %y
@@ -163,176 +301,298 @@ define amdgpu_kernel void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i3
ret void
}
-
-; FUNC-LABEL: {{^}}test_udivrem_v4:
-; EG-DAG: RECIP_UINT
-; EG-DAG: MULHI
-; EG-DAG: MULLO_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: MULHI
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: MULHI
-; EG-DAG: MULLO_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SETGE_UINT
-; EG-DAG: SETGE_UINT
-; EG-DAG: AND_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: RECIP_UINT
-; EG-DAG: MULHI
-; EG-DAG: MULLO_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: MULHI
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: MULHI
-; EG-DAG: MULLO_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SETGE_UINT
-; EG-DAG: SETGE_UINT
-; EG-DAG: AND_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: RECIP_UINT
-; EG-DAG: MULHI
-; EG-DAG: MULLO_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: MULHI
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: MULHI
-; EG-DAG: MULLO_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SETGE_UINT
-; EG-DAG: SETGE_UINT
-; EG-DAG: AND_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: RECIP_UINT
-; EG-DAG: MULHI
-; EG-DAG: MULLO_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: MULHI
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: MULHI
-; EG-DAG: MULLO_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SETGE_UINT
-; EG-DAG: SETGE_UINT
-; EG-DAG: AND_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: ADD_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-
-; SI-DAG: v_rcp_iflag_f32_e32
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_mul_lo_u32
-; SI-DAG: v_sub_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_mul_lo_u32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_rcp_iflag_f32_e32
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_mul_lo_u32
-; SI-DAG: v_sub_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_mul_lo_u32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_rcp_iflag_f32_e32
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_mul_lo_u32
-; SI-DAG: v_sub_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_mul_lo_u32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_rcp_iflag_f32_e32
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_mul_lo_u32
-; SI-DAG: v_sub_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_add_{{[iu]}}32_e32
-; SI-DAG: v_subrev_{{[iu]}}32_e32
-; SI-DAG: v_cndmask_b32_e64
-; SI-NOT: v_and_b32
-; SI: s_endpgm
define amdgpu_kernel void @test_udivrem_v4(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
+; R600-LABEL: test_udivrem_v4:
+; R600: ; %bb.0:
+; R600-NEXT: ALU 77, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+; R600-NEXT: ALU clause starting at 4:
+; R600-NEXT: RECIP_UINT * T0.X, KC0[5].X,
+; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[5].X,
+; R600-NEXT: SUB_INT T0.W, 0.0, PS,
+; R600-NEXT: MULHI * T0.Z, T0.X, KC0[5].X,
+; R600-NEXT: CNDE_INT * T0.W, PS, PV.W, T0.Y,
+; R600-NEXT: MULHI * T0.Y, PV.W, T0.X,
+; R600-NEXT: RECIP_UINT * T0.W, KC0[4].Y,
+; R600-NEXT: MULLO_INT * T1.X, PS, KC0[4].Y,
+; R600-NEXT: SUB_INT T1.W, 0.0, PS,
+; R600-NEXT: MULHI * T1.Y, T0.W, KC0[4].Y,
+; R600-NEXT: CNDE_INT T1.Z, PS, PV.W, T1.X, BS:VEC_021/SCL_122
+; R600-NEXT: ADD_INT T1.W, T0.X, T0.Y,
+; R600-NEXT: SUB_INT * T2.W, T0.X, T0.Y,
+; R600-NEXT: CNDE_INT T1.W, T0.Z, PV.W, PS,
+; R600-NEXT: MULHI * T0.X, PV.Z, T0.W,
+; R600-NEXT: MULHI * T0.Y, PV.W, KC0[4].X,
+; R600-NEXT: RECIP_UINT * T0.Z, KC0[4].Z,
+; R600-NEXT: MULLO_INT * T1.X, PS, KC0[4].Z,
+; R600-NEXT: SUB_INT T1.W, 0.0, PS,
+; R600-NEXT: MULHI * T1.Z, T0.Z, KC0[4].Z,
+; R600-NEXT: CNDE_INT T1.W, PS, PV.W, T1.X,
+; R600-NEXT: RECIP_UINT * T1.X, KC0[4].W,
+; R600-NEXT: MULHI * T1.W, PV.W, T0.Z,
+; R600-NEXT: ADD_INT T2.Z, T0.Z, PS,
+; R600-NEXT: SUB_INT T1.W, T0.Z, PS,
+; R600-NEXT: MULLO_INT * T0.Z, T1.X, KC0[4].W,
+; R600-NEXT: CNDE_INT T1.Z, T1.Z, PV.Z, PV.W,
+; R600-NEXT: SUB_INT T1.W, 0.0, PS,
+; R600-NEXT: MULHI * T2.X, T1.X, KC0[4].W,
+; R600-NEXT: CNDE_INT T1.W, PS, PV.W, T0.Z,
+; R600-NEXT: MULHI * T0.Z, PV.Z, KC0[3].Z,
+; R600-NEXT: MULHI * T1.Z, PV.W, T1.X,
+; R600-NEXT: ADD_INT T2.Z, T1.X, PS,
+; R600-NEXT: SUB_INT T1.W, T1.X, PS,
+; R600-NEXT: MULLO_INT * T0.Z, T0.Z, KC0[4].Z,
+; R600-NEXT: CNDE_INT T1.Z, T2.X, PV.Z, PV.W,
+; R600-NEXT: SUB_INT T1.W, KC0[3].Z, PS,
+; R600-NEXT: MULLO_INT * T0.Y, T0.Y, KC0[5].X,
+; R600-NEXT: SUB_INT T1.X, PV.W, KC0[4].Z,
+; R600-NEXT: SUB_INT T2.Y, KC0[4].X, PS,
+; R600-NEXT: ADD_INT T2.Z, T0.W, T0.X,
+; R600-NEXT: SUB_INT * T0.W, T0.W, T0.X,
+; R600-NEXT: MULHI * T0.X, T1.Z, KC0[3].W,
+; R600-NEXT: CNDE_INT T1.Y, T1.Y, T2.Z, T0.W,
+; R600-NEXT: SETGE_UINT T1.Z, T2.Y, KC0[5].X, BS:VEC_120/SCL_212
+; R600-NEXT: SETGE_UINT * T0.W, KC0[4].X, T0.Y, BS:VEC_021/SCL_122
+; R600-NEXT: MULLO_INT * T0.X, T0.X, KC0[4].W,
+; R600-NEXT: ADD_INT T2.X, T2.Y, KC0[5].X,
+; R600-NEXT: AND_INT T0.Y, T1.Z, T0.W,
+; R600-NEXT: SUB_INT T1.Z, T2.Y, KC0[5].X,
+; R600-NEXT: SUB_INT * T2.W, KC0[3].W, PS,
+; R600-NEXT: MULHI * T1.Y, T1.Y, KC0[3].Y,
+; R600-NEXT: ADD_INT T3.X, T2.W, KC0[4].W,
+; R600-NEXT: CNDE_INT T0.Y, T0.Y, T2.Y, T1.Z,
+; R600-NEXT: SETGE_UINT T1.Z, T2.W, KC0[4].W,
+; R600-NEXT: SETGE_UINT * T3.W, KC0[3].W, T0.X,
+; R600-NEXT: MULLO_INT * T0.X, T1.Y, KC0[4].Y,
+; R600-NEXT: SUB_INT T4.X, KC0[3].Y, PS,
+; R600-NEXT: AND_INT T1.Y, T1.Z, T3.W,
+; R600-NEXT: SUB_INT T1.Z, T2.W, KC0[4].W,
+; R600-NEXT: SETGE_UINT * T4.W, T1.W, KC0[4].Z, BS:VEC_201
+; R600-NEXT: SETGE_UINT * T5.W, KC0[3].Z, T0.Z,
+; R600-NEXT: AND_INT T5.X, T4.W, PV.W,
+; R600-NEXT: CNDE_INT T1.Y, T1.Y, T2.W, T1.Z, BS:VEC_210
+; R600-NEXT: SETGE_UINT T0.Z, T4.X, KC0[4].Y,
+; R600-NEXT: SETGE_UINT T2.W, KC0[3].Y, T0.X, BS:VEC_021/SCL_122
+; R600-NEXT: CNDE_INT * T0.W, T0.W, T2.X, T0.Y,
+; R600-NEXT: AND_INT T0.X, PV.Z, PV.W,
+; R600-NEXT: SUB_INT T2.Y, T4.X, KC0[4].Y,
+; R600-NEXT: CNDE_INT T0.Z, T3.W, T3.X, PV.Y,
+; R600-NEXT: CNDE_INT T3.W, PV.X, T1.W, T1.X,
+; R600-NEXT: ADD_INT * T1.W, T1.W, KC0[4].Z,
+; R600-NEXT: CNDE_INT T0.Y, T5.W, PS, PV.W,
+; R600-NEXT: CNDE_INT T1.W, PV.X, T4.X, PV.Y,
+; R600-NEXT: ADD_INT * T3.W, T4.X, KC0[4].Y,
+; R600-NEXT: CNDE_INT T0.X, T2.W, PS, PV.W,
+; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX6-LABEL: test_udivrem_v4:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s6, 0x4f800000
+; GFX6-NEXT: s_load_dwordx2 s[16:17], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s19, 0xf000
+; GFX6-NEXT: s_mov_b32 s18, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s13
+; GFX6-NEXT: v_cvt_f32_u32_e32 v7, s15
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_f32_e32 v0, s6, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, s6, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s12
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, s12
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0, v2
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
+; GFX6-NEXT: v_mul_hi_u32 v2, v2, v0
+; GFX6-NEXT: v_mul_lo_u32 v3, v1, s13
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v2, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT: v_mul_hi_u32 v2, v1, s13
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
+; GFX6-NEXT: v_mul_hi_u32 v0, v0, s8
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1]
+; GFX6-NEXT: v_mul_hi_u32 v2, v2, v1
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s12
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v2, v1
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s14
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
+; GFX6-NEXT: v_mul_hi_u32 v1, v1, s9
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s8, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_ge_u32_e64 s[4:5], s8, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s13
+; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v3
+; GFX6-NEXT: v_mul_f32_e32 v2, s6, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, s12, v3
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s12, v3
+; GFX6-NEXT: s_and_b64 vcc, s[2:3], s[4:5]
+; GFX6-NEXT: v_mul_lo_u32 v5, v2, s14
+; GFX6-NEXT: v_mul_hi_u32 v6, v2, s14
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[4:5]
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s9, v1
+; GFX6-NEXT: v_cmp_ge_u32_e64 s[2:3], s9, v1
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 0, v5
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[4:5]
+; GFX6-NEXT: v_mul_hi_u32 v1, v1, v2
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v3
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, s13, v3
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s13, v3
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v1, v2
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[4:5]
+; GFX6-NEXT: v_mul_hi_u32 v1, v1, s10
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v7
+; GFX6-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v5, v1, s14
+; GFX6-NEXT: v_mul_f32_e32 v1, s6, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, v3, s[2:3]
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s10, v5
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v3
+; GFX6-NEXT: v_mul_lo_u32 v4, v2, s15
+; GFX6-NEXT: v_mul_hi_u32 v6, v2, s15
+; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 0, v4
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v6
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[2:3]
+; GFX6-NEXT: v_mul_hi_u32 v4, v4, v2
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, s14, v3
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, v4, v2
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v7, s[2:3]
+; GFX6-NEXT: v_mul_hi_u32 v2, v2, s11
+; GFX6-NEXT: v_cmp_ge_u32_e64 s[2:3], s10, v5
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s14, v3
+; GFX6-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
+; GFX6-NEXT: v_mul_lo_u32 v5, v2, s15
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[2:3]
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s11, v5
+; GFX6-NEXT: v_cmp_ge_u32_e64 s[2:3], s11, v5
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v3
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, s15, v3
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s15, v3
+; GFX6-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[2:3]
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: test_udivrem_v4:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0x34
+; GFX8-NEXT: s_mov_b32 s16, 0x4f800000
+; GFX8-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s12
+; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s13
+; GFX8-NEXT: v_cvt_f32_u32_e32 v7, s15
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX8-NEXT: v_mul_f32_e32 v0, s16, v0
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_f32_e32 v1, s16, v1
+; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX8-NEXT: v_mul_lo_u32 v2, v0, s12
+; GFX8-NEXT: v_mul_hi_u32 v3, v0, s12
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v3
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[2:3]
+; GFX8-NEXT: v_mul_hi_u32 v2, v2, v0
+; GFX8-NEXT: v_mul_lo_u32 v3, v1, s13
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, v2, v0
+; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, v2, v0
+; GFX8-NEXT: v_mul_hi_u32 v2, v1, s13
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[2:3]
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0, v3
+; GFX8-NEXT: v_mul_hi_u32 v0, v0, s8
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1]
+; GFX8-NEXT: v_mul_hi_u32 v2, v2, v1
+; GFX8-NEXT: v_mul_lo_u32 v0, v0, s12
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, v2, v1
+; GFX8-NEXT: v_subrev_u32_e32 v1, vcc, v2, v1
+; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s14
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
+; GFX8-NEXT: v_mul_hi_u32 v1, v1, s9
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s8, v0
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX8-NEXT: v_cmp_ge_u32_e64 s[4:5], s8, v0
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, s13
+; GFX8-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v3
+; GFX8-NEXT: v_mul_f32_e32 v2, s16, v2
+; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, s12, v3
+; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s12, v3
+; GFX8-NEXT: s_and_b64 vcc, s[2:3], s[4:5]
+; GFX8-NEXT: v_mul_lo_u32 v5, v2, s14
+; GFX8-NEXT: v_mul_hi_u32 v6, v2, s14
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[4:5]
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s9, v1
+; GFX8-NEXT: v_cmp_ge_u32_e64 s[2:3], s9, v1
+; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 0, v5
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[4:5]
+; GFX8-NEXT: v_mul_hi_u32 v1, v1, v2
+; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v3
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, s13, v3
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s13, v3
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, v1, v2
+; GFX8-NEXT: v_subrev_u32_e32 v1, vcc, v1, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[4:5]
+; GFX8-NEXT: v_mul_hi_u32 v1, v1, s10
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v7
+; GFX8-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX8-NEXT: v_mul_lo_u32 v5, v1, s14
+; GFX8-NEXT: v_mul_f32_e32 v1, s16, v2
+; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v4, v3, s[2:3]
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s10, v5
+; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v3
+; GFX8-NEXT: v_mul_lo_u32 v4, v2, s15
+; GFX8-NEXT: v_mul_hi_u32 v6, v2, s15
+; GFX8-NEXT: v_sub_u32_e32 v7, vcc, 0, v4
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v6
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[2:3]
+; GFX8-NEXT: v_mul_hi_u32 v4, v4, v2
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, s14, v3
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, v4, v2
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, v4, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v7, s[2:3]
+; GFX8-NEXT: v_mul_hi_u32 v2, v2, s11
+; GFX8-NEXT: v_cmp_ge_u32_e64 s[2:3], s10, v5
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s14, v3
+; GFX8-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
+; GFX8-NEXT: v_mul_lo_u32 v5, v2, s15
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[2:3]
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s11, v5
+; GFX8-NEXT: v_cmp_ge_u32_e64 s[2:3], s11, v5
+; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v3
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, s15, v3
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s15, v3
+; GFX8-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[2:3]
+; GFX8-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
%result0 = udiv <4 x i32> %x, %y
store <4 x i32> %result0, <4 x i32> addrspace(1)* %out
%result1 = urem <4 x i32> %x, %y
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