[PATCH] D79794: Change the INLINEASM_BR MachineInstr to be a non-terminating instruction.

[Bill Wendling via Phabricator via llvm-commits]

void added a comment.

@nathanchance & @nickdesaulniers: I forgot the post scheduler. Try the patch below.

  diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
  index 0f21c97a30f..e28d25bbfae 100644
  --- a/llvm/lib/CodeGen/MachineScheduler.cpp
  +++ b/llvm/lib/CodeGen/MachineScheduler.cpp
  @@ -443,7 +443,8 @@ static bool isSchedBoundary(MachineBasicBlock::iterator MI,
                               MachineBasicBlock *MBB,
                               MachineFunction *MF,
                               const TargetInstrInfo *TII) {
  -  return MI->isCall() || TII->isSchedulingBoundary(*MI, MBB, *MF);
  +  return MI->isCall() || MI->getOpcode() == TargetOpcode::INLINEASM_BR ||
  +      TII->isSchedulingBoundary(*MI, MBB, *MF);
   }
   
   /// A region of an MBB for scheduling.
  diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp
  index b85f00a61ea..1a2a1d753cd 100644
  --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp
  +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp
  @@ -338,7 +338,8 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
         // Calls are not scheduling boundaries before register allocation, but
         // post-ra we don't gain anything by scheduling across calls since we
         // don't need to worry about register pressure.
  -      if (MI.isCall() || TII->isSchedulingBoundary(MI, &MBB, Fn)) {
  +      if (MI.isCall() || MI.getOpcode() == TargetOpcode::INLINEASM_BR ||
  +          TII->isSchedulingBoundary(MI, &MBB, Fn)) {
           Scheduler.enterRegion(&MBB, I, Current, CurrentCount - Count);
           Scheduler.setEndIndex(CurrentCount);
           Scheduler.schedule();
  diff --git a/llvm/test/CodeGen/X86/callbr-asm-outputs.ll b/llvm/test/CodeGen/X86/callbr-asm-outputs.ll
  index 61baa31074e..a4447bc15f1 100644
  --- a/llvm/test/CodeGen/X86/callbr-asm-outputs.ll
  +++ b/llvm/test/CodeGen/X86/callbr-asm-outputs.ll
  @@ -41,6 +41,7 @@ define i32 @test2(i32 %out1, i32 %out2) {
   ; CHECK-NEXT:    .cfi_offset %edi, -8
   ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edi
   ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
  +; CHECK-NEXT:    movl $-1, %eax
   ; CHECK-NEXT:    cmpl %edi, %esi
   ; CHECK-NEXT:    jge .LBB1_2
   ; CHECK-NEXT:  # %bb.1: # %if.then
  @@ -49,7 +50,6 @@ define i32 @test2(i32 %out1, i32 %out2) {
   ; CHECK-NEXT:    testl %edi, %esi
   ; CHECK-NEXT:    jne .Ltmp1
   ; CHECK-NEXT:    #NO_APP
  -; CHECK-NEXT:    movl $-1, %eax
   ; CHECK-NEXT:    jmp .LBB1_3
   ; CHECK-NEXT:  .LBB1_2: # %if.else
   ; CHECK-NEXT:    #APP
  @@ -57,7 +57,6 @@ define i32 @test2(i32 %out1, i32 %out2) {
   ; CHECK-NEXT:    testl %esi, %edi
   ; CHECK-NEXT:    jne .Ltmp2
   ; CHECK-NEXT:    #NO_APP
  -; CHECK-NEXT:    movl $-1, %eax
   ; CHECK-NEXT:  .LBB1_3:
   ; CHECK-NEXT:    movl %esi, %eax
   ; CHECK-NEXT:    addl %edi, %eax




Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D79794/new/

https://reviews.llvm.org/D79794