[PATCH] D82234: [amdgpu] Fix REL32 relocations with negative offsets.

[Michael Liao via Phabricator via llvm-commits]

hliao created this revision.
hliao added reviewers: rampitec, arsenm.
Herald added subscribers: llvm-commits, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.
hliao added a comment.

This patch only handles the case where that offset is representable in a 32-bit signed integer. For a  generic 64-bit offset out of range of 32-bit integer, we need to revise the relocation spec to enhance REL32_HI from the orginal

  (S +A - P) >> 32

to

  (S + (A << 32) - P) >> 32

where A is that 32-bit sword addend. In fact, we split a 64-bit offset into low 32-bit addend used in REL32_LO and high 32-bit addend used in REL32_HI. However, that needs changes in more than components. As that's the rate case,  I want to address the current critical issue first and will start the discussion on relocation changes.


- The offset should be treated as a signed one.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82234

Files:
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/rel32.ll


Index: llvm/test/CodeGen/AMDGPU/rel32.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/rel32.ll
@@ -0,0 +1,12 @@
+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
+
+ at g = protected local_unnamed_addr addrspace(4) externally_initialized global i32 0, align 4
+
+; CHECK-LABEL: rel32_neg_offset:
+; CHECK: s_getpc_b64 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{]}}
+; CHECK: s_add_u32 s[[LO]], s[[LO]], g at rel32@lo-4
+; CHECK: s_addc_u32 s[[HI]], s[[HI]], g at rel32@hi-4
+define i32 addrspace(4)* @rel32_neg_offset() {
+  %r = getelementptr i32, i32 addrspace(4)* @g, i64 -2
+  ret i32 addrspace(4)* %r
+}
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5461,8 +5461,9 @@
 
 static SDValue
 buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV,
-                        const SDLoc &DL, unsigned Offset, EVT PtrVT,
+                        const SDLoc &DL, int64_t Offset, EVT PtrVT,
                         unsigned GAFlags = SIInstrInfo::MO_NONE) {
+  assert(isInt<32>(Offset + 4) && "32-bit offset is expected!");
   // In order to support pc-relative addressing, the PC_ADD_REL_OFFSET SDNode is
   // lowered to the following code sequence:
   //
Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -61,9 +61,9 @@
   bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
                       MachineIRBuilder &B) const;
 
-  bool buildPCRelGlobalAddress(
-    Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
-    unsigned Offset, unsigned GAFlags = SIInstrInfo::MO_NONE) const;
+  bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B,
+                               const GlobalValue *GV, int64_t Offset,
+                               unsigned GAFlags = SIInstrInfo::MO_NONE) const;
 
   bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
                            MachineIRBuilder &B) const;
Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2003,10 +2003,12 @@
   return true;
 }
 
-bool AMDGPULegalizerInfo::buildPCRelGlobalAddress(
-  Register DstReg, LLT PtrTy,
-  MachineIRBuilder &B, const GlobalValue *GV,
-  unsigned Offset, unsigned GAFlags) const {
+bool AMDGPULegalizerInfo::buildPCRelGlobalAddress(Register DstReg, LLT PtrTy,
+                                                  MachineIRBuilder &B,
+                                                  const GlobalValue *GV,
+                                                  int64_t Offset,
+                                                  unsigned GAFlags) const {
+  assert(isInt<32>(Offset + 4) && "32-bit offset is expected!");
   // In order to support pc-relative addressing, SI_PC_ADD_REL_OFFSET is lowered
   // to the following code sequence:
   //


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