[PATCH] D81914: [AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:7038-7041
+      const TargetRegisterClass *RC = RI.getPhysRegClass(PhysReg);
+      unsigned Width = RI.getRegSizeInBits(*RC);
+      if (RI.isSGPRClass(RC)) {
+        if (Width == 32) {
----------------
This shouldn't consider the register class of the physical register. Only the register class of the virtual register matters (plus getPhysRegClass is really slow), and you shouldn't need to get the size and check if it's an SGPR.

Something like:
RC = MRI.getRegClass(VirtReg);
if (RC->contains(m0) || RC->contains(exec) ...)

or alternatively
RC->hasSuperClassEq(AMDGPU::SReg_64RegClass) 
...
RC->hasSuperClassEq(AMDGPU::SReg_32RegClass)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81914/new/

https://reviews.llvm.org/D81914