[llvm] 88f722c - [DSE, MSSA] Enable XFAIL'd merge-stores.ll test (NFC).
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 19 04:16:39 PDT 2020
Author: Florian Hahn
Date: 2020-06-19T12:10:47+01:00
New Revision: 88f722c269a571f1e5ef7bcd16f15c4973eb6c73
URL: https://github.com/llvm/llvm-project/commit/88f722c269a571f1e5ef7bcd16f15c4973eb6c73
DIFF: https://github.com/llvm/llvm-project/commit/88f722c269a571f1e5ef7bcd16f15c4973eb6c73.diff
LOG: [DSE,MSSA] Enable XFAIL'd merge-stores.ll test (NFC).
All cases in the test are supported now, it only still failed because an
over-eager regex match not accounting for `, align ` being added to each
load/store now.
Added:
Modified:
llvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores.ll
index b09904e5a27d..7643c3ba5b9e 100644
--- a/llvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores.ll
+++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; XFAIL: *
; RUN: opt -dse -enable-dse-memoryssa -enable-dse-partial-store-merging -S < %s | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-f128:128:128-n8:16:32:64"
@@ -190,16 +189,16 @@ define void @PR34074(i32* %x, i64* %y) {
define void @PR36129(i32* %P, i32* %Q) {
; CHECK-LABEL: @PR36129(
-; CHECK-NEXT: store i32 1, i32* [[P:%.*]]
+; CHECK-NEXT: store i32 1, i32* [[P:%.*]], align 4
; CHECK-NEXT: [[P2:%.*]] = bitcast i32* [[P]] to i8*
-; CHECK-NEXT: store i32 2, i32* [[Q:%.*]]
-; CHECK-NEXT: store i8 3, i8* [[P2]]
+; CHECK-NEXT: store i32 2, i32* [[Q:%.*]], align 4
+; CHECK-NEXT: store i8 3, i8* [[P2]], align 1
; CHECK-NEXT: ret void
;
- store i32 1, i32* %P
+ store i32 1, i32* %P, align 4
%P2 = bitcast i32* %P to i8*
- store i32 2, i32* %Q
- store i8 3, i8* %P2
+ store i32 2, i32* %Q, align 4
+ store i8 3, i8* %P2, align 1
ret void
}
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