[PATCH] D77152: [SelectionDAG] Better legalization for FSHL and FSHR

[Jay Foad via Phabricator via llvm-commits]

foad marked 4 inline comments as done.
foad added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:6053
+  return false;
+}
+
----------------
RKSimon wrote:
> You might be able to use ISD::matchUnaryPredicate to do some of this - so you just need to provide a predicate lambda
Nice tip, thanks!


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Comment at: llvm/test/CodeGen/AMDGPU/fshl.ll:25
+; SI-NEXT:    s_or_b32 s0, s0, s1
+; SI-NEXT:    v_mov_b32_e32 v0, s0
 ; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
----------------
arsenm wrote:
> RKSimon wrote:
> > IIRC amdgpu supports fshr but not fshl - could we do more in the expansion to handle this - invert the shift amount and use the legal opcode?
> I think this is what was here before; the alignbit is gone
> 
> I was also wondering if there was a tricky way to use the 32 bit version in the 64 bit implementation 
If we had a test like fshl_i32 but with the inputs in vgprs then I guess it would show a regression here.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77152/new/

https://reviews.llvm.org/D77152