[PATCH] D81578: [CodeGen] Fix warnings in getVectorTypeBreakdown
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 18 02:09:21 PDT 2020
This revision was automatically updated to reflect the committed changes.
david-arm marked an inline comment as done.
Closed by commit rG7e30ef77f674: [CodeGen] Fix warnings in getVectorTypeBreakdown (authored by david-arm).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81578/new/
https://reviews.llvm.org/D81578
Files:
llvm/include/llvm/Support/TypeSize.h
llvm/lib/CodeGen/TargetLoweringBase.cpp
Index: llvm/lib/CodeGen/TargetLoweringBase.cpp
===================================================================
--- llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -1474,14 +1474,14 @@
MVT DestVT = getRegisterType(Context, NewVT);
RegisterVT = DestVT;
- unsigned NewVTSize = NewVT.getSizeInBits();
- // Convert sizes such as i33 to i64.
- if (!isPowerOf2_32(NewVTSize))
- NewVTSize = NextPowerOf2(NewVTSize);
-
- if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
+ if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
+ TypeSize NewVTSize = NewVT.getSizeInBits();
+ // Convert sizes such as i33 to i64.
+ if (!isPowerOf2_32(NewVTSize.getKnownMinSize()))
+ NewVTSize = NewVTSize.NextPowerOf2();
return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
+ }
// Otherwise, promotion or legal types use the same number of registers as
// the vector decimated to the appropriate level.
Index: llvm/include/llvm/Support/TypeSize.h
===================================================================
--- llvm/include/llvm/Support/TypeSize.h
+++ llvm/include/llvm/Support/TypeSize.h
@@ -229,6 +229,10 @@
TypeSize operator/(int64_t RHS) const {
return { MinSize / RHS, IsScalable };
}
+
+ TypeSize NextPowerOf2() const {
+ return TypeSize(llvm::NextPowerOf2(MinSize), IsScalable);
+ }
};
/// Returns a TypeSize with a known minimum size that is the next integer
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