[PATCH] D81914: [AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D81914#2097845 <https://reviews.llvm.org/D81914#2097845>, @critson wrote:

> In D81914#2095875 <https://reviews.llvm.org/D81914#2095875>, @arsenm wrote:
>
> > Can you try to constrain the class of the virtual register earlier to avoid this from happening instead? I think that should avoid this coming up (e.g.  we do MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0RegClass) already to try avoiding m0 spills, plus in foldMemoryOperandImpl to avoid another problem when spills are optimized out)
>
>
> I could look at that, but it seems advantageous to be able to spill and restore EXEC directly when we at the point of spilling SGPRs?


As a reserved register, ppilling of exec should be impossible. The only situations where it "spills" are when a copy was coalesced of another register that spilled. We should be able to satisfy everything by register class constraints. Even if that weren't the case,  I would prefer to proceed by first constraining the register classes, and then applying the more complex fix if it turns out there are still cases that can't be avoided


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81914/new/

https://reviews.llvm.org/D81914