[PATCH] D81914: [AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills

[Carl Ritson via Phabricator via llvm-commits]

critson added a comment.

In D81914#2095875 <https://reviews.llvm.org/D81914#2095875>, @arsenm wrote:

> Can you try to constrain the class of the virtual register earlier to avoid this from happening instead? I think that should avoid this coming up (e.g.  we do MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0RegClass) already to try avoiding m0 spills, plus in foldMemoryOperandImpl to avoid another problem when spills are optimized out)


I could look at that, but it seems advantageous to be able to spill and restore EXEC directly when we at the point of spilling SGPRs?



================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:866
 
+// VGPR lanes cannot be read directly into EXEC registers.
+// This function generates moves via a temporary SGPR or VGPR.
----------------
arsenm wrote:
> I'm pretty sure this used to be true, so this should depend on the subtarget?
If we can establish at what point it became unsupported, but it seems it does not work on anything recent. 
I have verified that it does not work on gfx900 or gfx1010.
If I get a chance I will test gfx7.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81914/new/

https://reviews.llvm.org/D81914