[PATCH] D81993: [AArch64][GlobalISel] Add artifact combine for sext(trunc(sextload)) -> trunc/copy

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added reviewers: paquette, arsenm.
aemerson added a project: LLVM.
Herald added subscribers: danielkiss, kristof.beyls, rovka, wdng.

On AArch64 we generate redundant G_SEXTs or G_SEXT_INREGs because of this.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81993

Files:
  llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
 ---
 name:            test_sext_inreg
 body: |
@@ -13,3 +13,19 @@
     %2:_(s32) = G_SEXT_INREG %0(s32), 7
     $w0 = COPY %2(s32)
 ...
+---
+name:            test_combine_sext_trunc_of_sextload
+body: |
+  bb.0.entry:
+    liveins: $w0, $w1
+    ; CHECK-LABEL: name: test_combine_sext_trunc_of_sextload
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SEXTLOAD]](s64)
+    ; CHECK: $w0 = COPY [[TRUNC]](s32)
+    %0:_(p0) = COPY $x0
+    %1:_(s64) = G_SEXTLOAD %0:_(p0) :: (load 2)
+    %2:_(s16) = G_TRUNC %1:_(s64)
+    %3:_(s32) = G_SEXT %2:_(s16)
+    $w0 = COPY %3(s32)
+...
Index: llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
===================================================================
--- llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -169,6 +169,20 @@
       LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
       LLT SrcTy = MRI.getType(SrcReg);
       uint64_t SizeInBits = SrcTy.getScalarSizeInBits();
+
+      // If the source is a G_SEXTLOAD from the same bit width, then we don't
+      // need any extend at all, just a truncate.
+      if (auto *LoadMI =
+              getOpcodeDef(TargetOpcode::G_SEXTLOAD, TruncSrc, MRI)) {
+        const auto &MMO = **LoadMI->memoperands_begin();
+        if (MMO.getSizeInBits() == SizeInBits) {
+          Builder.buildAnyExtOrTrunc(DstReg, LoadMI->getOperand(0).getReg());
+          UpdatedDefs.push_back(DstReg);
+          markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
+          return true;
+        }
+      }
+
       Builder.buildInstr(
           TargetOpcode::G_SEXT_INREG, {DstReg},
           {Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), SizeInBits});


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