[llvm] e35ba09 - [gicombiner] Allow generated combiners to store additional members
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 16 14:48:30 PDT 2020
Author: Daniel Sanders
Date: 2020-06-16T14:47:04-07:00
New Revision: e35ba09961c89faa4801b45c33b70a8b3a64fe84
URL: https://github.com/llvm/llvm-project/commit/e35ba09961c89faa4801b45c33b70a8b3a64fe84
DIFF: https://github.com/llvm/llvm-project/commit/e35ba09961c89faa4801b45c33b70a8b3a64fe84.diff
LOG: [gicombiner] Allow generated combiners to store additional members
Summary:
Adds the ability to add members to a generated combiner via
a State base class. In the current AArch64PreLegalizerCombiner
this is used to make Helper available without having to
provide it to every call.
As part of this, split the command line processing into a
separate object so that it still only runs once even though
the generated combiner is constructed more frequently.
Depends on D81862
Reviewers: aditya_nandakumar, bogner, volkan, aemerson, paquette, arsenm
Reviewed By: arsenm
Subscribers: jvesely, wdng, nhaehnle, kristof.beyls, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D81863
Added:
Modified:
llvm/include/llvm/Target/GlobalISel/Combine.td
llvm/lib/Target/AArch64/AArch64Combine.td
llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
llvm/utils/TableGen/GICombinerEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 7803ce1b51ab..eeb2761faeb9 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -40,6 +40,9 @@ class GICombinerHelper<string classname, list<GICombine> rules>
// The name of a run-time compiler option that will be generated to disable
// specific rules within this combiner.
string DisableRuleOption = ?;
+ // The state class to inherit from (if any). The generated helper will inherit
+ // from this class and will forward arguments to its constructors.
+ string StateClass = "";
// Any additional arguments that should be appended to the tryCombine*().
list<GICombinerHelperArg> AdditionalArguments =
[GICombinerHelperArg<"CombinerHelper &", "Helper">];
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index 072008b07ced..1e39db5a984a 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -22,6 +22,8 @@ def AArch64PreLegalizerCombinerHelper: GICombinerHelper<
elide_br_by_inverting_cond,
fconstant_to_constant]> {
let DisableRuleOption = "aarch64prelegalizercombiner-disable-rule";
+ let StateClass = "AArch64PreLegalizerCombinerHelperState";
+ let AdditionalArguments = [];
}
// Matchdata for combines which replace a G_SHUFFLE_VECTOR with a
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index 3217068c4a64..9fbe185dce2a 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -372,7 +372,7 @@ class AArch64PostLegalizerCombinerInfo : public CombinerInfo {
MachineDominatorTree *MDT;
public:
- AArch64GenPostLegalizerCombinerHelper Generated;
+ AArch64GenPostLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
AArch64PostLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
GISelKnownBits *KB,
@@ -380,7 +380,7 @@ class AArch64PostLegalizerCombinerInfo : public CombinerInfo {
: CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
/*LegalizerInfo*/ nullptr, EnableOpt, OptSize, MinSize),
KB(KB), MDT(MDT) {
- if (!Generated.parseCommandLineOption())
+ if (!GeneratedRuleCfg.parseCommandLineOption())
report_fatal_error("Invalid rule identifier");
}
@@ -394,6 +394,7 @@ bool AArch64PostLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
const auto *LI =
MI.getParent()->getParent()->getSubtarget().getLegalizerInfo();
CombinerHelper Helper(Observer, B, KB, MDT, LI);
+ AArch64GenPostLegalizerCombinerHelper Generated(GeneratedRuleCfg);
return Generated.tryCombineAll(Observer, MI, B, Helper);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index 1e5658960407..9a1f200d5222 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -53,6 +53,15 @@ static void applyFConstantToConstant(MachineInstr &MI) {
MI.eraseFromParent();
}
+class AArch64PreLegalizerCombinerHelperState {
+protected:
+ CombinerHelper &Helper;
+
+public:
+ AArch64PreLegalizerCombinerHelperState(CombinerHelper &Helper)
+ : Helper(Helper) {}
+};
+
#define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
#include "AArch64GenPreLegalizeGICombiner.inc"
#undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
@@ -65,16 +74,15 @@ namespace {
class AArch64PreLegalizerCombinerInfo : public CombinerInfo {
GISelKnownBits *KB;
MachineDominatorTree *MDT;
+ AArch64GenPreLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
public:
- AArch64GenPreLegalizerCombinerHelper Generated;
-
AArch64PreLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
GISelKnownBits *KB, MachineDominatorTree *MDT)
: CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
/*LegalizerInfo*/ nullptr, EnableOpt, OptSize, MinSize),
KB(KB), MDT(MDT) {
- if (!Generated.parseCommandLineOption())
+ if (!GeneratedRuleCfg.parseCommandLineOption())
report_fatal_error("Invalid rule identifier");
}
@@ -86,6 +94,7 @@ bool AArch64PreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
MachineInstr &MI,
MachineIRBuilder &B) const {
CombinerHelper Helper(Observer, B, KB, MDT);
+ AArch64GenPreLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper);
switch (MI.getOpcode()) {
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
@@ -105,7 +114,7 @@ bool AArch64PreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
}
}
- if (Generated.tryCombineAll(Observer, MI, B, Helper))
+ if (Generated.tryCombineAll(Observer, MI, B))
return true;
switch (MI.getOpcode()) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
index 974358f616fa..29203eb7df22 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
@@ -233,7 +233,7 @@ class AMDGPUPostLegalizerCombinerInfo : public CombinerInfo {
MachineDominatorTree *MDT;
public:
- AMDGPUGenPostLegalizerCombinerHelper Generated;
+ AMDGPUGenPostLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
AMDGPUPostLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
const AMDGPULegalizerInfo *LI,
@@ -241,7 +241,7 @@ class AMDGPUPostLegalizerCombinerInfo : public CombinerInfo {
: CombinerInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
/*LegalizerInfo*/ LI, EnableOpt, OptSize, MinSize),
KB(KB), MDT(MDT) {
- if (!Generated.parseCommandLineOption())
+ if (!GeneratedRuleCfg.parseCommandLineOption())
report_fatal_error("Invalid rule identifier");
}
@@ -253,6 +253,7 @@ bool AMDGPUPostLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
MachineInstr &MI,
MachineIRBuilder &B) const {
CombinerHelper Helper(Observer, B, KB, MDT);
+ AMDGPUGenPostLegalizerCombinerHelper Generated(GeneratedRuleCfg);
if (Generated.tryCombineAll(Observer, MI, B, Helper))
return true;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
index 1c337afadd43..800ad2039f0e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
@@ -42,14 +42,14 @@ class AMDGPUPreLegalizerCombinerInfo : public CombinerInfo {
MachineDominatorTree *MDT;
public:
- AMDGPUGenPreLegalizerCombinerHelper Generated;
+ AMDGPUGenPreLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
AMDGPUPreLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
GISelKnownBits *KB, MachineDominatorTree *MDT)
: CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
/*LegalizerInfo*/ nullptr, EnableOpt, OptSize, MinSize),
KB(KB), MDT(MDT) {
- if (!Generated.parseCommandLineOption())
+ if (!GeneratedRuleCfg.parseCommandLineOption())
report_fatal_error("Invalid rule identifier");
}
@@ -61,6 +61,7 @@ bool AMDGPUPreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
MachineInstr &MI,
MachineIRBuilder &B) const {
CombinerHelper Helper(Observer, B, KB, MDT);
+ AMDGPUGenPreLegalizerCombinerHelper Generated(GeneratedRuleCfg);
if (Generated.tryCombineAll(Observer, MI, B, Helper))
return true;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index 18c58c6ff5db..71d82679b3ff 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -44,7 +44,7 @@ class AMDGPURegBankCombinerInfo : public CombinerInfo {
MachineDominatorTree *MDT;
public:
- AMDGPUGenRegBankCombinerHelper Generated;
+ AMDGPUGenRegBankCombinerHelperRuleConfig GeneratedRuleCfg;
AMDGPURegBankCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
const AMDGPULegalizerInfo *LI,
@@ -52,7 +52,7 @@ class AMDGPURegBankCombinerInfo : public CombinerInfo {
: CombinerInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
/*LegalizerInfo*/ LI, EnableOpt, OptSize, MinSize),
KB(KB), MDT(MDT) {
- if (!Generated.parseCommandLineOption())
+ if (!GeneratedRuleCfg.parseCommandLineOption())
report_fatal_error("Invalid rule identifier");
}
@@ -64,6 +64,7 @@ bool AMDGPURegBankCombinerInfo::combine(GISelChangeObserver &Observer,
MachineInstr &MI,
MachineIRBuilder &B) const {
CombinerHelper Helper(Observer, B, KB, MDT);
+ AMDGPUGenRegBankCombinerHelper Generated(GeneratedRuleCfg);
if (Generated.tryCombineAll(Observer, MI, B, Helper))
return true;
diff --git a/llvm/utils/TableGen/GICombinerEmitter.cpp b/llvm/utils/TableGen/GICombinerEmitter.cpp
index 761ca4b52614..151b18dbe034 100644
--- a/llvm/utils/TableGen/GICombinerEmitter.cpp
+++ b/llvm/utils/TableGen/GICombinerEmitter.cpp
@@ -743,7 +743,8 @@ void GICombinerEmitter::generateCodeForTree(raw_ostream &OS,
const Record &RuleDef = Rule->getDef();
OS << Indent << "// Rule: " << RuleDef.getName() << "\n"
- << Indent << "if (!isRuleDisabled(" << Rule->getID() << ")) {\n";
+ << Indent << "if (!RuleConfig->isRuleDisabled(" << Rule->getID()
+ << ")) {\n";
CodeExpansions Expansions;
for (const auto &VarBinding : Leaf.var_bindings()) {
@@ -897,13 +898,29 @@ void GICombinerEmitter::run(raw_ostream &OS) {
<< "#endif // ifdef " << Name.upper() << "_GENCOMBINERHELPER_DEPS\n\n";
OS << "#ifdef " << Name.upper() << "_GENCOMBINERHELPER_H\n"
- << "class " << getClassName() << " {\n"
+ << "class " << getClassName() << "RuleConfig {\n"
<< " SparseBitVector<> DisabledRules;\n"
<< "\n"
<< "public:\n"
<< " bool parseCommandLineOption();\n"
<< " bool isRuleDisabled(unsigned ID) const;\n"
<< " bool setRuleDisabled(StringRef RuleIdentifier);\n"
+ << "\n"
+ << "};\n"
+ << "\n"
+ << "class " << getClassName();
+ StringRef StateClass = Combiner->getValueAsString("StateClass");
+ if (!StateClass.empty())
+ OS << " : public " << StateClass;
+ OS << " {\n"
+ << " const " << getClassName() << "RuleConfig *RuleConfig;\n"
+ << "\n"
+ << "public:\n"
+ << " template<typename ... Args>" << getClassName() << "(const "
+ << getClassName() << "RuleConfig &RuleConfig, Args &&... args) : ";
+ if (!StateClass.empty())
+ OS << StateClass << "(std::forward<Args>(args)...), ";
+ OS << "RuleConfig(&RuleConfig) {}\n"
<< "\n"
<< " bool tryCombineAll(\n"
<< " GISelChangeObserver &Observer,\n"
@@ -916,7 +933,7 @@ void GICombinerEmitter::run(raw_ostream &OS) {
emitNameMatcher(OS);
OS << "bool " << getClassName()
- << "::setRuleDisabled(StringRef RuleIdentifier) {\n"
+ << "RuleConfig::setRuleDisabled(StringRef RuleIdentifier) {\n"
<< " std::pair<StringRef, StringRef> RangePair = "
"RuleIdentifier.split('-');\n"
<< " if (!RangePair.second.empty()) {\n"
@@ -941,7 +958,7 @@ void GICombinerEmitter::run(raw_ostream &OS) {
<< "}\n";
OS << "bool " << getClassName()
- << "::isRuleDisabled(unsigned RuleID) const {\n"
+ << "RuleConfig::isRuleDisabled(unsigned RuleID) const {\n"
<< " return DisabledRules.test(RuleID);\n"
<< "}\n";
OS << "#endif // ifdef " << Name.upper() << "_GENCOMBINERHELPER_H\n\n";
@@ -956,7 +973,7 @@ void GICombinerEmitter::run(raw_ostream &OS) {
<< " cl::Hidden,\n"
<< " cl::cat(GICombinerOptionCategory));\n"
<< "\n"
- << "bool " << getClassName() << "::parseCommandLineOption() {\n"
+ << "bool " << getClassName() << "RuleConfig::parseCommandLineOption() {\n"
<< " for (const auto &Identifier : " << Name << "Option)\n"
<< " if (!setRuleDisabled(Identifier))\n"
<< " return false;\n"
@@ -973,7 +990,7 @@ void GICombinerEmitter::run(raw_ostream &OS) {
<< " MachineFunction *MF = MBB->getParent();\n"
<< " MachineRegisterInfo &MRI = MF->getRegInfo();\n"
<< " SmallVector<MachineInstr *, 8> MIs = { &MI };\n\n"
- << " (void)MBB; (void)MF; (void)MRI;\n\n";
+ << " (void)MBB; (void)MF; (void)MRI; (void)RuleConfig;\n\n";
OS << " // Match data\n";
for (const auto &Rule : Rules)
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