[PATCH] D81638: AMDGPU/GlobalISel: Fix 96 and 128 local loads and stores

[Mirko Brkusanin via Phabricator via llvm-commits]

mbrkusanin updated this revision to Diff 271122.
mbrkusanin retitled this revision from "AMDGPU/GlobalISel: Fix 96-bit local loads" to "AMDGPU/GlobalISel: Fix 96 and 128 local loads and stores".
mbrkusanin edited the summary of this revision.
mbrkusanin added a comment.

Looking at ISA .pdf docs for SI (gfx6) and onward I have not found any requirements for alignments on local loads and stores. There are mentions of dword alignment for reads and writes of dword and larger for buffer instructions but nothing more specific for LDS or GDS. SDag likes to break down ds_read/write_b128 in certain cases but does not know about b96. It seems to me that the code was not updated since SI.
Now b96 and b128 will be picked for align 4 and larger (align 2 and 1 are broken down same way as before). Furthermore, there are several Vulkan conformance tests that have align 4 loads and stores (96 and 128) that will now pass.

Alternative solution would be to break them down to ds_read/write_b64/b32 when we're not sure. But I don't have a test to check if this is necessary.

Since all changes are in .td files this should not cause you any problems with rewriting load/store legality rules.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81638/new/

https://reviews.llvm.org/D81638

Files:
  llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
  llvm/lib/Target/AMDGPU/DSInstructions.td
  llvm/lib/Target/AMDGPU/SIInstrInfo.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll

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