[PATCH] D81914: [AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Can you try to constrain the class of the virtual register earlier to avoid this from happening instead? I think that should avoid this coming up (e.g.  we do MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0RegClass) already to try avoiding m0 spills, plus in foldMemoryOperandImpl to avoid another problem when spills are optimized out)



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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:866
 
+// VGPR lanes cannot be read directly into EXEC registers.
+// This function generates moves via a temporary SGPR or VGPR.
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I'm pretty sure this used to be true, so this should depend on the subtarget?


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https://reviews.llvm.org/D81914