[PATCH] D81901: GlobalISel: Implement bitcast action for G_EXTRACT_VECTOR_ELEMENT

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: aemerson, aditya_nandakumar, paquette, dsanders, kerbowa, foad, rampitec.
Herald added subscribers: hiraditya, tpr, rovka, nhaehnle, wdng, jvesely.
Herald added a project: LLVM.
arsenm edited the summary of this revision.
arsenm updated this revision to Diff 270936.
arsenm added a comment.

Fix missing part of example comment


For AMDGPU, vectors with elements < 32 bits should be indexed in
32-bit elements and the desired bits extracted from there. For
elements > 64-bits, these should be reduce to 64/32 elements to enable
the normal dynamic indexing paths.

      

In the dynamic index cases, this produces shorter code most of the
time. This does immediately regress the constant index cases, but this
should be fixed once we have the most basic of shift combines.

      

The element size > 64 case is pretty much ported from the exisiting
DAG implementation for extract element promote. The increasing element size 
case is new.


https://reviews.llvm.org/D81901

Files:
  llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir

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