[llvm] 576fa5a - [AMDGPU] make ubsan happy with unsigned left shift
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 15 17:21:21 PDT 2020
Author: Stanislav Mekhanoshin
Date: 2020-06-15T17:21:10-07:00
New Revision: 576fa5a50c8509977835031d190f8906e1dbb075
URL: https://github.com/llvm/llvm-project/commit/576fa5a50c8509977835031d190f8906e1dbb075
DIFF: https://github.com/llvm/llvm-project/commit/576fa5a50c8509977835031d190f8906e1dbb075.diff
LOG: [AMDGPU] make ubsan happy with unsigned left shift
Fixes UBSAN error after rG9ee272f13d88f090817235ef4f91e56bb2a153d6
A trivial signed/unsigned shift.
Added:
Modified:
llvm/lib/Target/AMDGPU/SMInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 252f191a2f66..df21c864ccad 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -860,7 +860,7 @@ let OtherPredicates = [HasNoSMemTimeInst] in {
def : GCNPat <
(i64 (readcyclecounter)),
(REG_SEQUENCE SReg_64,
- (S_GETREG_B32 getHwRegImm<HWREG.SHADER_CYCLES, 0, -12>.ret), sub0,
+ (S_GETREG_B32 -26595), sub0,
(S_MOV_B32 (i32 0)), sub1)
>;
} // let OtherPredicates = [HasNoSMemTimeInst]
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