[PATCH] D81547: [X86][SSE] MatchVectorAllZeroTest - handle OR vector reductions
Sanjay Patel via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 15 13:19:04 PDT 2020
spatel added inline comments.
================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:21395
// CMP(MOVMSK(PCMPEQB(X,0))).
static SDValue MatchVectorAllZeroTest(SDValue Op, ISD::CondCode CC,
+ const SDLoc &DL,
----------------
Can we assert that CC is ISD::SETEQ or ISD::SETNE here?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81547/new/
https://reviews.llvm.org/D81547
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