[llvm] 57c9dc0 - [PowerPC] Do not add the relocation addend to the instruction encoding

[Stefan Pintilie via llvm-commits]

Author: Stefan Pintilie
Date: 2020-06-15T09:51:34-05:00
New Revision: 57c9dc0521ab7ed7fbff0a25da16312e5a410e66

URL: https://github.com/llvm/llvm-project/commit/57c9dc0521ab7ed7fbff0a25da16312e5a410e66
DIFF: https://github.com/llvm/llvm-project/commit/57c9dc0521ab7ed7fbff0a25da16312e5a410e66.diff

LOG: [PowerPC] Do not add the relocation addend to the instruction encoding

We should not be adding the relocation addend to the instruction encoding.
This patch removes that and sets those bits to zero.

Differential Revision: https://reviews.llvm.org/D81082

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
    llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
index 017ee948dab7..5b9a05486144 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
@@ -219,7 +219,8 @@ PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
     Fixups.push_back(
         MCFixup::create(0, Expr,
                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
-    // There is no offset to return so just return 0.
+    // Put zero in the location of the immediate. The linker will fill in the
+    // correct value based on the relocation.
     return 0;
   }
   case MCExpr::Binary: {
@@ -242,6 +243,7 @@ PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(LHS);
     (void)SRE;
     const MCConstantExpr *CE = cast<MCConstantExpr>(RHS);
+    assert(isInt<34>(CE->getValue()) && "Value must fit in 34 bits.");
 
     // Currently these are the only valid PCRelative Relocations.
     assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
@@ -251,9 +253,9 @@ PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
     Fixups.push_back(
         MCFixup::create(0, Expr,
                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
-    assert(isInt<34>(CE->getValue()) && "Value must fit in 34 bits.");
-    // Return the offset that should be added to the relocation by the linker.
-    return (CE->getValue() & 0x3FFFFFFFFUL) | RegBits;
+    // Put zero in the location of the immediate. The linker will fill in the
+    // correct value based on the relocation.
+    return 0;
     }
   }
 }

diff  --git a/llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll b/llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll
index 44820b633573..373b339d45e1 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll
@@ -16,7 +16,7 @@ define dso_local signext i32 @getElementLocal7() local_unnamed_addr {
 ; CHECK-S-NEXT:    plwa r3, array2 at PCREL+28(0), 1
 ; CHECK-S-NEXT:    blr
 ; CHECK-O-LABEL: <getElementLocal7>:
-; CHECK-O:         00 00 10 04 1c 00 60 a4       plwa 3, 28(0), 1
+; CHECK-O:         00 00 10 04 00 00 60 a4       plwa 3, 0(0), 1
 ; CHECK-O-NEXT:    0000000000000000:  R_PPC64_PCREL34      array2+0x1c
 ; CHECK-O-NEXT:    20 00 80 4e                   blr
 entry:
@@ -30,7 +30,7 @@ define dso_local signext i32 @getElementLocalNegative() local_unnamed_addr {
 ; CHECK-S-NEXT:    plwa r3, array2 at PCREL-8(0), 1
 ; CHECK-S-NEXT:    blr
 ; CHECK-O-LABEL: <getElementLocalNegative>:
-; CHECK-O:         ff ff 13 04 f8 ff 60 a4       plwa 3, -8(0), 1
+; CHECK-O:         00 00 10 04 00 00 60 a4       plwa 3, 0(0), 1
 ; CHECK-O-NEXT:    0000000000000020:  R_PPC64_PCREL34      array2-0x8
 ; CHECK-O-NEXT:    20 00 80 4e                   blr
 entry: