[llvm] 163162a - [PowerPC] fold a bug for rlwinm folding when with full mask.

[Chen Zheng via llvm-commits]

Author: Chen Zheng
Date: 2020-06-14T21:27:01-04:00
New Revision: 163162a0a41213ce6ca052f6ab5822669d2391ac

URL: https://github.com/llvm/llvm-project/commit/163162a0a41213ce6ca052f6ab5822669d2391ac
DIFF: https://github.com/llvm/llvm-project/commit/163162a0a41213ce6ca052f6ab5822669d2391ac.diff

LOG: [PowerPC] fold a bug for rlwinm folding when with full mask.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D81006

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    llvm/test/CodeGen/PowerPC/fold-rlwinm.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 457f4c1aa85b..e70f04e72ed5 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -3421,8 +3421,7 @@ bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
     int64_t ME = MI.getOperand(4).getImm();
     APInt InVal(32, SExtImm, true);
     InVal = InVal.rotl(SH);
-    // Set the bits (        MB + 32        ) to (        ME + 32        ).
-    uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
+    APInt Mask = APInt::getBitsSetWithWrap(32, 32 - ME - 1, 32 - MB);
     InVal &= Mask;
     // Can't replace negative values with an LI as that will sign-extend
     // and not clear the left bits. If we're setting the CR bit, we will use

diff  --git a/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir b/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
index dc69dcb11d25..ded5329a46cc 100644
--- a/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
+++ b/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
@@ -168,3 +168,17 @@ body: |
     ; CHECK: %3:gprc = RLWINM %2, 19, 10, 20
     BLR8 implicit $lr8, implicit $rm
 ...
+---
+name: testFoldRLWINMLIWrapMask
+#CHECK: name: testFoldRLWINMLIWrapMask
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3
+    %0:gprc = COPY $x3
+    %1:gprc = LI 100
+    ; CHECK: %2:gprc = LI 200
+    %2:gprc = RLWINM %1:gprc, 1, 3, 2
+    STW %2:gprc, %0:gprc, 100
+    BLR8 implicit $lr8, implicit $rm
+...