[PATCH] D81805: [RISCV] Fix isStoreToStackSlot

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

I have been unable to come up with a test that shows any change (I may check LNT to see if something changes), so ideas are welcome here.

However I'd expect this function return true (at least for now in RISC-V) for every instruction created in `RISCVInstrInfo::storeRegToStackSlot`. Conceptually (not part of the current patch) like this.

  diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  index dc212d9cde2..8a28a21a29e 100644
  --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  @@ -131,10 +131,14 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     else
       llvm_unreachable("Can't store this register to stack slot");
   
  -  BuildMI(MBB, I, DL, get(Opcode))
  +  MachineInstr *MI = BuildMI(MBB, I, DL, get(Opcode))
         .addReg(SrcReg, getKillRegState(IsKill))
         .addFrameIndex(FI)
         .addImm(0);
  +
  +  int Dummy;
  +  (void)Dummy;
  +  assert(this->isStoreToStackSlot(*MI, Dummy) && "This is exactly a store to a stack slot");
   }


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D81805/new/

https://reviews.llvm.org/D81805