[llvm] 93264a2 - [X86] Enable the EVEX->VEX compression pass at -O0.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 13 12:29:23 PDT 2020
Author: Craig Topper
Date: 2020-06-13T12:29:04-07:00
New Revision: 93264a2e4fc21b6e5efa705198d577cccef6dac8
URL: https://github.com/llvm/llvm-project/commit/93264a2e4fc21b6e5efa705198d577cccef6dac8
DIFF: https://github.com/llvm/llvm-project/commit/93264a2e4fc21b6e5efa705198d577cccef6dac8.diff
LOG: [X86] Enable the EVEX->VEX compression pass at -O0.
A lot of what EVEX->VEX does is equivalent to what the
prioritization in the assembly parser does. When an AVX mnemonic
is used without any EVEX features or XMM16-31, the parser will
pick the VEX encoding.
Since codegen doesn't go through the parser, we should also
use VEX instructions when we can so that the code coming out of
integrated assembler matches what you'd get from outputing an
assembly listing and parsing it.
The pass early outs if AVX isn't enabled and uses TSFlags to
check for EVEX instructions before doing the more costly table
lookups. Hopefully that's enough to keep this from impacting
-O0 compile times.
Added:
Modified:
llvm/lib/Target/X86/X86TargetMachine.cpp
llvm/test/CodeGen/X86/O0-pipeline.ll
llvm/test/CodeGen/X86/fast-isel-vecload.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index ec7a12c63056..c159728ed1dd 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -520,8 +520,8 @@ void X86PassConfig::addPreEmitPass() {
addPass(createX86FixupBWInsts());
addPass(createX86PadShortFunctions());
addPass(createX86FixupLEAs());
- addPass(createX86EvexToVexInsts());
}
+ addPass(createX86EvexToVexInsts());
addPass(createX86DiscriminateMemOpsPass());
addPass(createX86InsertPrefetchPass());
addPass(createX86InsertX87waitPass());
diff --git a/llvm/test/CodeGen/X86/O0-pipeline.ll b/llvm/test/CodeGen/X86/O0-pipeline.ll
index ea9399871100..a1cd828abeab 100644
--- a/llvm/test/CodeGen/X86/O0-pipeline.ll
+++ b/llvm/test/CodeGen/X86/O0-pipeline.ll
@@ -59,6 +59,7 @@
; CHECK-NEXT: Implement the 'patchable-function' attribute
; CHECK-NEXT: X86 Indirect Branch Tracking
; CHECK-NEXT: X86 vzeroupper inserter
+; CHECK-NEXT: Compressing EVEX instrs to VEX encoding when possibl
; CHECK-NEXT: X86 Discriminate Memory Operands
; CHECK-NEXT: X86 Insert Cache Prefetches
; CHECK-NEXT: X86 insert wait instruction
diff --git a/llvm/test/CodeGen/X86/fast-isel-vecload.ll b/llvm/test/CodeGen/X86/fast-isel-vecload.ll
index 1cdeae96b2db..7e8c6537f59c 100644
--- a/llvm/test/CodeGen/X86/fast-isel-vecload.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-vecload.ll
@@ -13,20 +13,10 @@ define <16 x i8> @test_v16i8(<16 x i8>* %V) {
; SSE-NEXT: movdqa (%rdi), %xmm0
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v16i8:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqa (%rdi), %xmm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v16i8:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqa (%rdi), %xmm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v16i8:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqa64 (%rdi), %xmm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v16i8:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %xmm0
+; AVX-NEXT: retq
entry:
%0 = load <16 x i8>, <16 x i8>* %V, align 16
ret <16 x i8> %0
@@ -38,20 +28,10 @@ define <8 x i16> @test_v8i16(<8 x i16>* %V) {
; SSE-NEXT: movdqa (%rdi), %xmm0
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v8i16:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqa (%rdi), %xmm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v8i16:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqa (%rdi), %xmm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v8i16:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqa64 (%rdi), %xmm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v8i16:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %xmm0
+; AVX-NEXT: retq
entry:
%0 = load <8 x i16>, <8 x i16>* %V, align 16
ret <8 x i16> %0
@@ -63,20 +43,10 @@ define <4 x i32> @test_v4i32(<4 x i32>* %V) {
; SSE-NEXT: movdqa (%rdi), %xmm0
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v4i32:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqa (%rdi), %xmm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v4i32:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqa (%rdi), %xmm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v4i32:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqa64 (%rdi), %xmm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v4i32:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %xmm0
+; AVX-NEXT: retq
entry:
%0 = load <4 x i32>, <4 x i32>* %V, align 16
ret <4 x i32> %0
@@ -88,20 +58,10 @@ define <2 x i64> @test_v2i64(<2 x i64>* %V) {
; SSE-NEXT: movdqa (%rdi), %xmm0
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v2i64:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqa (%rdi), %xmm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v2i64:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqa (%rdi), %xmm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v2i64:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqa64 (%rdi), %xmm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v2i64:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %xmm0
+; AVX-NEXT: retq
entry:
%0 = load <2 x i64>, <2 x i64>* %V, align 16
ret <2 x i64> %0
@@ -113,20 +73,10 @@ define <16 x i8> @test_v16i8_unaligned(<16 x i8>* %V) {
; SSE-NEXT: movdqu (%rdi), %xmm0
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v16i8_unaligned:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqu (%rdi), %xmm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v16i8_unaligned:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqu (%rdi), %xmm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v16i8_unaligned:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqu64 (%rdi), %xmm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v16i8_unaligned:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqu (%rdi), %xmm0
+; AVX-NEXT: retq
entry:
%0 = load <16 x i8>, <16 x i8>* %V, align 4
ret <16 x i8> %0
@@ -138,20 +88,10 @@ define <8 x i16> @test_v8i16_unaligned(<8 x i16>* %V) {
; SSE-NEXT: movdqu (%rdi), %xmm0
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v8i16_unaligned:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqu (%rdi), %xmm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v8i16_unaligned:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqu (%rdi), %xmm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v8i16_unaligned:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqu64 (%rdi), %xmm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v8i16_unaligned:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqu (%rdi), %xmm0
+; AVX-NEXT: retq
entry:
%0 = load <8 x i16>, <8 x i16>* %V, align 4
ret <8 x i16> %0
@@ -163,20 +103,10 @@ define <4 x i32> @test_v4i32_unaligned(<4 x i32>* %V) {
; SSE-NEXT: movdqu (%rdi), %xmm0
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v4i32_unaligned:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqu (%rdi), %xmm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v4i32_unaligned:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqu (%rdi), %xmm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v4i32_unaligned:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqu64 (%rdi), %xmm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v4i32_unaligned:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqu (%rdi), %xmm0
+; AVX-NEXT: retq
entry:
%0 = load <4 x i32>, <4 x i32>* %V, align 4
ret <4 x i32> %0
@@ -188,20 +118,10 @@ define <2 x i64> @test_v2i64_unaligned(<2 x i64>* %V) {
; SSE-NEXT: movdqu (%rdi), %xmm0
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v2i64_unaligned:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqu (%rdi), %xmm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v2i64_unaligned:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqu (%rdi), %xmm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v2i64_unaligned:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqu64 (%rdi), %xmm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v2i64_unaligned:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqu (%rdi), %xmm0
+; AVX-NEXT: retq
entry:
%0 = load <2 x i64>, <2 x i64>* %V, align 4
ret <2 x i64> %0
@@ -273,20 +193,10 @@ define <16 x i8> @test_v16i8_abi_alignment(<16 x i8>* %V) {
; SSE-NEXT: movdqa (%rdi), %xmm0
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v16i8_abi_alignment:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqa (%rdi), %xmm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v16i8_abi_alignment:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqa (%rdi), %xmm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v16i8_abi_alignment:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqa64 (%rdi), %xmm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v16i8_abi_alignment:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %xmm0
+; AVX-NEXT: retq
entry:
%0 = load <16 x i8>, <16 x i8>* %V
ret <16 x i8> %0
@@ -298,20 +208,10 @@ define <8 x i16> @test_v8i16_abi_alignment(<8 x i16>* %V) {
; SSE-NEXT: movdqa (%rdi), %xmm0
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v8i16_abi_alignment:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqa (%rdi), %xmm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v8i16_abi_alignment:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqa (%rdi), %xmm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v8i16_abi_alignment:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqa64 (%rdi), %xmm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v8i16_abi_alignment:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %xmm0
+; AVX-NEXT: retq
entry:
%0 = load <8 x i16>, <8 x i16>* %V
ret <8 x i16> %0
@@ -323,20 +223,10 @@ define <4 x i32> @test_v4i32_abi_alignment(<4 x i32>* %V) {
; SSE-NEXT: movdqa (%rdi), %xmm0
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v4i32_abi_alignment:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqa (%rdi), %xmm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v4i32_abi_alignment:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqa (%rdi), %xmm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v4i32_abi_alignment:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqa64 (%rdi), %xmm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v4i32_abi_alignment:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %xmm0
+; AVX-NEXT: retq
entry:
%0 = load <4 x i32>, <4 x i32>* %V
ret <4 x i32> %0
@@ -348,20 +238,10 @@ define <2 x i64> @test_v2i64_abi_alignment(<2 x i64>* %V) {
; SSE-NEXT: movdqa (%rdi), %xmm0
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v2i64_abi_alignment:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqa (%rdi), %xmm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v2i64_abi_alignment:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqa (%rdi), %xmm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v2i64_abi_alignment:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqa64 (%rdi), %xmm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v2i64_abi_alignment:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %xmm0
+; AVX-NEXT: retq
entry:
%0 = load <2 x i64>, <2 x i64>* %V
ret <2 x i64> %0
@@ -404,20 +284,10 @@ define <32 x i8> @test_v32i8(<32 x i8>* %V) {
; SSE-NEXT: movaps 16(%rdi), %xmm1
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v32i8:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqa (%rdi), %ymm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v32i8:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqa (%rdi), %ymm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v32i8:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqa64 (%rdi), %ymm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v32i8:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %ymm0
+; AVX-NEXT: retq
entry:
%0 = load <32 x i8>, <32 x i8>* %V, align 32
ret <32 x i8> %0
@@ -430,20 +300,10 @@ define <16 x i16> @test_v16i16(<16 x i16>* %V) {
; SSE-NEXT: movaps 16(%rdi), %xmm1
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v16i16:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqa (%rdi), %ymm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v16i16:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqa (%rdi), %ymm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v16i16:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqa64 (%rdi), %ymm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v16i16:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %ymm0
+; AVX-NEXT: retq
entry:
%0 = load <16 x i16>, <16 x i16>* %V, align 32
ret <16 x i16> %0
@@ -456,20 +316,10 @@ define <8 x i32> @test_v8i32(<8 x i32>* %V) {
; SSE-NEXT: movaps 16(%rdi), %xmm1
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v8i32:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqa (%rdi), %ymm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v8i32:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqa (%rdi), %ymm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v8i32:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqa64 (%rdi), %ymm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v8i32:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %ymm0
+; AVX-NEXT: retq
entry:
%0 = load <8 x i32>, <8 x i32>* %V, align 32
ret <8 x i32> %0
@@ -482,20 +332,10 @@ define <4 x i64> @test_v4i64(<4 x i64>* %V) {
; SSE-NEXT: movaps 16(%rdi), %xmm1
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v4i64:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqa (%rdi), %ymm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v4i64:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqa (%rdi), %ymm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v4i64:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqa64 (%rdi), %ymm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v4i64:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %ymm0
+; AVX-NEXT: retq
entry:
%0 = load <4 x i64>, <4 x i64>* %V, align 32
ret <4 x i64> %0
@@ -508,20 +348,10 @@ define <32 x i8> @test_v32i8_unaligned(<32 x i8>* %V) {
; SSE-NEXT: movups 16(%rdi), %xmm1
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v32i8_unaligned:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqu (%rdi), %ymm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v32i8_unaligned:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqu (%rdi), %ymm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v32i8_unaligned:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqu64 (%rdi), %ymm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v32i8_unaligned:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqu (%rdi), %ymm0
+; AVX-NEXT: retq
entry:
%0 = load <32 x i8>, <32 x i8>* %V, align 4
ret <32 x i8> %0
@@ -534,20 +364,10 @@ define <16 x i16> @test_v16i16_unaligned(<16 x i16>* %V) {
; SSE-NEXT: movups 16(%rdi), %xmm1
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v16i16_unaligned:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqu (%rdi), %ymm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v16i16_unaligned:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqu (%rdi), %ymm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v16i16_unaligned:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqu64 (%rdi), %ymm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v16i16_unaligned:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqu (%rdi), %ymm0
+; AVX-NEXT: retq
entry:
%0 = load <16 x i16>, <16 x i16>* %V, align 4
ret <16 x i16> %0
@@ -560,20 +380,10 @@ define <8 x i32> @test_v8i32_unaligned(<8 x i32>* %V) {
; SSE-NEXT: movups 16(%rdi), %xmm1
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v8i32_unaligned:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqu (%rdi), %ymm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v8i32_unaligned:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqu (%rdi), %ymm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v8i32_unaligned:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqu64 (%rdi), %ymm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v8i32_unaligned:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqu (%rdi), %ymm0
+; AVX-NEXT: retq
entry:
%0 = load <8 x i32>, <8 x i32>* %V, align 4
ret <8 x i32> %0
@@ -586,20 +396,10 @@ define <4 x i64> @test_v4i64_unaligned(<4 x i64>* %V) {
; SSE-NEXT: movups 16(%rdi), %xmm1
; SSE-NEXT: retq
;
-; AVXONLY-LABEL: test_v4i64_unaligned:
-; AVXONLY: # %bb.0: # %entry
-; AVXONLY-NEXT: vmovdqu (%rdi), %ymm0
-; AVXONLY-NEXT: retq
-;
-; KNL-LABEL: test_v4i64_unaligned:
-; KNL: # %bb.0: # %entry
-; KNL-NEXT: vmovdqu (%rdi), %ymm0
-; KNL-NEXT: retq
-;
-; SKX-LABEL: test_v4i64_unaligned:
-; SKX: # %bb.0: # %entry
-; SKX-NEXT: vmovdqu64 (%rdi), %ymm0
-; SKX-NEXT: retq
+; AVX-LABEL: test_v4i64_unaligned:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovdqu (%rdi), %ymm0
+; AVX-NEXT: retq
entry:
%0 = load <4 x i64>, <4 x i64>* %V, align 4
ret <4 x i64> %0
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