[PATCH] D81710: [amdgpu] Skip OR combining on 64-bit integer before legalizing ops.

[Michael Liao via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGec02635d104c: [amdgpu] Skip OR combining on 64-bit integer before legalizing ops. (authored by hliao).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81710/new/

https://reviews.llvm.org/D81710

Files:
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/fshr.ll


Index: llvm/test/CodeGen/AMDGPU/fshr.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/fshr.ll
+++ llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -763,7 +763,7 @@
 ; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
 ; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
 ; SI-NEXT:    v_and_b32_e32 v2, v9, v1
-; SI-NEXT:    v_alignbit_b32 v1, v2, v0, 16
+; SI-NEXT:    v_alignbit_b32 v1, v1, v0, 16
 ; SI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-LABEL: v_fshr_v3i16:
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -8958,7 +8958,7 @@
     }
   }
 
-  if (VT != MVT::i64)
+  if (VT != MVT::i64 || DCI.isBeforeLegalizeOps())
     return SDValue();
 
   // TODO: This could be a generic combine with a predicate for extracting the


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