[PATCH] D81710: [amdgpu] Skip OR combining on 64-bit integer before legalizing ops.
Michael Liao via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 11 19:48:08 PDT 2020
hliao created this revision.
hliao added reviewers: arsenm, rampitec.
Herald added subscribers: llvm-commits, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D81710
Files:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/test/CodeGen/AMDGPU/fshr.ll
Index: llvm/test/CodeGen/AMDGPU/fshr.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/fshr.ll
+++ llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -763,7 +763,7 @@
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; SI-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
; SI-NEXT: v_and_b32_e32 v2, v9, v1
-; SI-NEXT: v_alignbit_b32 v1, v2, v0, 16
+; SI-NEXT: v_alignbit_b32 v1, v1, v0, 16
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_fshr_v3i16:
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -8906,7 +8906,7 @@
}
}
- if (VT != MVT::i64)
+ if (VT != MVT::i64 || DCI.isBeforeLegalizeOps())
return SDValue();
// TODO: This could be a generic combine with a predicate for extracting the
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