[PATCH] D81537: [PowerPC] Support constrained fp operation for scalar fptosi/fptoui
Qing Shan Zhang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 11 19:15:54 PDT 2020
steven.zhang added a comment.
Some code style comments.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:8253
const SDLoc &dl) const {
- assert(Op.getOperand(0).getValueType().isFloatingPoint());
- SDValue Src = Op.getOperand(0);
-
- if (Src.getValueType() == MVT::f32)
- Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
-
- SDValue Tmp;
- switch (Op.getSimpleValueType().SimpleTy) {
- default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
- case MVT::i32:
- Tmp = DAG.getNode(
- Op.getOpcode() == ISD::FP_TO_SINT
- ? PPCISD::FCTIWZ
- : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
- dl, MVT::f64, Src);
- Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
- break;
- case MVT::i64:
- assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
- "i64 FP_TO_UINT is supported only with FPCVT");
- Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
- PPCISD::FCTIDUZ,
- dl, MVT::f64, Src);
- Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
- break;
- }
- return Tmp;
+ SDValue Tmp = convertFPToInt(Op, DAG, Subtarget);
+ return getFPNode(PPCISD::MFVSR, Op.getSimpleValueType().SimpleTy, Tmp,
----------------
Don't use Tmp but with some meaningful name.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:8254
+ SDValue Tmp = convertFPToInt(Op, DAG, Subtarget);
+ return getFPNode(PPCISD::MFVSR, Op.getSimpleValueType().SimpleTy, Tmp,
+ Op.getOperand(0), DAG, Op->isStrictFPOpcode());
----------------
Op.getValueType() ?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81537/new/
https://reviews.llvm.org/D81537
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