[PATCH] D80437: [CodeGen] Let computeKnownBits do something sensible for scalable vectors
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 11 00:37:47 PDT 2020
This revision was automatically updated to reflect the committed changes.
Closed by commit rGbd97342a0c2c: [CodeGen] Let computeKnownBits do something sensible for scalable vectors (authored by david-arm).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80437/new/
https://reviews.llvm.org/D80437
Files:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-scalar-base-vector-indexes.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-32bit-scaled-offsets.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-32bit-unscaled-offsets.ll
llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
llvm/test/CodeGen/AArch64/sve-masked-ldst-trunc.ll
llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
llvm/test/CodeGen/AArch64/sve-setcc.ll
llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp
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