[PATCH] D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:524
+                                      CallConv))
+    return;
   EVT ValueVT = Val.getValueType();
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pratlucas wrote:
> efriedma wrote:
> > I'm not sure I understand why the standard getCopyFromParts/getCopyToParts codepath doesn't work. Is the issue that it uses FP_ROUND/FP_EXTEND to promote from f16 to f32?
> Yes, the issue is the usage of FP_ROUND/FP_EXTEND indeed. Those cause the argument to be converted from f16 into f32 - with a `vcvtb.f16.f32` for instance - instead of simply being placed the value in the LSBs as required by the AAPCS.
That makes sense.

It feels a little weird to have a TLI method to do the splitting, as opposed to adding an extra check to the shared codepath, but I guess this way is more flexible if someone else needs a similar change in the future.

One other thing to consider is that we could make f16 a "legal" type for all ARM subtargets with floating-point registers, regardless of whether the target actually has native f16 arithmetic instructions. We do this on AArch64.  That would reduce the number of different ways to handle f16 values, and I think this change would be unnecessary.


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:916
       ExtendKind = ISD::ZERO_EXTEND;
-
     getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part],
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(Accidental change?)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75169/new/

https://reviews.llvm.org/D75169