[PATCH] D81506: [X86] Automatically harden inline assembly RET instructions against Load Value Injection (LVI)

[Matthew Riley via Phabricator via llvm-commits]

mattdr accepted this revision.
mattdr added a comment.

LGTM, one question about source locations



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Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3199
+                                          /*BaseReg=*/Basereg, /*IndexReg=*/0,
+                                          /*Scale=*/1, SMLoc{}, SMLoc{}, 0);
+    ShlInst.setOpcode(X86::SHL64mi);
----------------
Seems like this will have implications for debugging. Can we copy the SMLoc from the original instruction, for this and for the other MCInsts we're creating?


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