[PATCH] D81524: AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D81524#2085006 <https://reviews.llvm.org/D81524#2085006>, @mbrkusanin wrote:

> What about DS_READ? Following are also broken:
>
>   define <3 x i32> @v_load_lds_v3i32_align1(<3 x i32> addrspace(3)* %ptr) {
>     %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 1
>     ret <3 x i32> %load
>   }
>  
>   define <3 x i32> @v_load_lds_v3i32_align2(<3 x i32> addrspace(3)* %ptr) {
>     %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 2
>     ret <3 x i32> %load
>   }
>  
>   define <3 x i32> @v_load_lds_v3i32_align4(<3 x i32> addrspace(3)* %ptr) {
>     %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 4
>     ret <3 x i32> %load
>   }
>  
>   define <3 x i32> @v_load_lds_v3i32_align8(<3 x i32> addrspace(3)* %ptr) {
>     %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 8
>     ret <3 x i32> %load
>   }
>  
>   define <3 x i32> @v_load_lds_v3i32_align16(<3 x i32> addrspace(3)* %ptr) {
>     %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 16
>     ret <3 x i32> %load
>   }
>
>
> It can be done with the same code in applyMappingLoad just by checking:
>
>    if (PtrBank == &AMDGPU::VGPRRegBank) {
>       if (LoadSize != 96)
>         return false;
>  
>       Register PtrReg = MI.getOperand(1).getReg();
>       const LLT PtrTy = MRI.getType(PtrReg);
>  
>       if (PtrTy.getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
>        ...
>     }
>   }
>
>
> and using VGPR bank in
>
>   ApplyRegBankMapping O(*this, MRI, &AMDGPU::VGPRRegBank);
>
>
> But should it select ds_read_b96 instead? SDag does not select it either.


This case should be handled in the regular legalizer since it isn't contextually dependent on whether the pointer is SGPR or VGPR


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