[PATCH] D80437: [CodeGen] Let computeKnownBits do something sensible for scalable vectors

[David Sherwood via Phabricator via llvm-commits]

david-arm updated this revision to Diff 269790.
david-arm added a comment.
Herald added a subscriber: arphaman.

Hi @efriedma, I tried to find some pre-existing folds that we were doing before my patch, but couldn't find anything. The problem is that fundamentally many of these functions need to understand SPLAT_VECTORs in order to return something known. I tried adding SPLAT_VECTOR support to isConstOrConstSplat, since that allowed us to call MaskedValueIsZero a bit more. However, we then end up crashing in SimplifyDemandedBits. However, I do understand your concern so I have added a unit test that confirms we pretend we know nothing. This patch kills off the last remaining warnings in quite a few tests, so I have added checks for no warnings in those files.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80437/new/

https://reviews.llvm.org/D80437

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-scalar-base-vector-indexes.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-32bit-scaled-offsets.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-32bit-unscaled-offsets.ll
  llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
  llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
  llvm/test/CodeGen/AArch64/sve-masked-ldst-trunc.ll
  llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
  llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
  llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
  llvm/test/CodeGen/AArch64/sve-setcc.ll
  llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp

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